Method of manufacturing semiconductor integrated circuit devices

Details Method of manufacturing semiconductor integrated circuit devices Method of manufacturing semiconductor integrated circuit devices

1981-12-02

1983-10-11

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29577C, 29578, 29580, 148175, 156628, 156647, 156649, 156657, 357 44, 357 49, 357 56, H01L 2176, H01L 2120

Patent

active

044083866

ABSTRACT:
Spaced recesses are formed in a surface of a low impurity concentration P type single-crystal substrate by using a mask. A P type impurity is diffused at a high concentration into an entire surface of the substrate including the recesses to form a P type diffused layer, and an N type layer is epitaxially grown on the P type diffused layer. Then, mask layers are formed on bottom surfaces of the recesses in the epitaxially grown N type layer and this N type layer is anisotropically etched by using the mask layers to form island regions in the recesses. After removing the mask layers, N type diffused layers are formed to cover the island regions. An insulating film (SiO.sub.2) acting to isolate completed transistor elements is formed on the P and N type diffused layers, and a polycrystalline silicon layer acting as a support of a dielectrically isolated integrated circuit device is formed on the insulating film. Then, the rear surface of the single-crystal silicon substrate is ground off to expose the insulating film. MOS or bipolar type transistor elements are formed in the island regions to obtain a dielectrically isolated semiconductor integrated device.

REFERENCES:
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patent: 3721588 (1973-03-01), Hays
patent: 3813584 (1974-05-01), Davidsohn et al.
patent: 3895392 (1975-07-01), Polata et al.
patent: 3953255 (1976-04-01), Combs
patent: 4017341 (1977-04-01), Suzuki et al.
patent: 4056413 (1977-11-01), Yoshimura
patent: 4089021 (1978-05-01), Sato et al.
patent: 4290831 (1981-09-01), Ports et al.
1973 International Electron Devices Meeting Technical Digest, Dec. 1973, pp. 41-43.
"Metal Bathtubs in Microcircuits Reduce Collector Resistance", Electronic Equipment Engineering, Dec. 1964, pp. 18-20.
Davidsohn et al., "Dielectric Isolated Integrated Circuit . . . Processes", Proc. IEEE, vol. 57, No. 9, Sep. 1969, pp. 1532-1537.
Wu, L. L., "Doped P & N Pockets for Complementary FETS", I.B.M. Tech. Discl. Bull., vol. 15, No. 7, Dec. 1972, p. 2279.

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