Fishing – trapping – and vermin destroying
Patent
1989-06-13
1990-05-15
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437225, 437905, 156643, 156646, 156662, 148DIG51, 148DIG131, 20419232, 20419235, 252372, H01L 2100, H01L 2102, H01L 21285, C23F 100
Patent
active
049258133
ABSTRACT:
A method of manufacturing semiconductor devices comprising at least a reactive ion etching step of a so-called substrate formed by semiconductor compounds having the general formulae Ga.sub.1-x As.sub.x In.sub.1-y P.sub.y, in which formulae x and y are the concentrations and lie between 0 and 1, this method comprising for carrying out this etching step a masking system of the said substrate cooperating with a flow of reacting gases, characterized in that the masking system is formed by a first metallic layer of titanium (Ti) of small thickness, on which a second metallic layer of nickel (Ni) is disposed having a thickness of about ten times larger, and in that the flow of reacting gases is formed by the mixture of the gases Cl.sub.2 /CH.sub.4 /H.sub.2 /Ar, in which mixture Cl.sub.2 is present in a quantity of about a quarter of the quantities of CH.sub.4 and Ar, as far as the partial pressures in the etching chamber are concerned.
Application: Manufacture of optoelectronic devices of III-V materials.
REFERENCES:
patent: 4467521 (1984-08-01), Spooner et al.
patent: 4771017 (1988-09-01), Tobin et al.
patent: 4840922 (1989-06-01), Kobayashi et al.
patent: 4861423 (1989-08-01), Carriere et al.
Furuya, F., Crystallographic Facets Chemically Etched in GaInAsP/InP for Integrated Optics, Electronic Letters, vol. 17, Aug. 20, 1981, pp. 582-583.
Aspnes, D., Chemical Etching and Cleaning Procedures for Si, Ge, and Some III-V Compound Semiconductors, Appl. Phys. Lett., 39(4), Aug. 15, 1981, pp. 316-318.
Bertrand, P., XPS Study of Chemically Etched GaAs and InP, J. Vac. Sci & Tech., 18(1), 1981, pp 28-33.
Adachi, S., InGaAsP/InP Buried-Heterostructure Lasers (.lambda.=5 .mu.m) with Chemically Etched Mirrors, J. Appl. Phys., 52(9), Sep. 1981, pp. 5843-5845.
DiLorenzo, J., An In-Situ Etch for the CVD Growth of GaAs: The `He-Etch`, Inst. Phys. Conf. Ser. No. 24, 1975, pp. 362-368.
Dobbs, B., A Technique for Uniform Etching of Polished Gallium Phosphide, J. Electrochem. Soc. (USA), vol. 125, No. 2, Feb. 1978, p. 347.
Kambayash, T., Chemical Etching of InP and GaInAsP for Fabricating Laser Diodes and Integrated Optical Circuits, Japanese Jour. of Appl. Phys., Jan. 1980, pp. 79-85.
Auger Jean-Marc
Autier Philippe
Everhart B.
Hearn Brian E.
Spain Norman N.
U.S. Philips Corporation
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