Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-06-18
2004-05-11
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S455000, C438S459000
Reexamination Certificate
active
06734040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices and, in particular but not exclusively, to a method of manufacturing hermetically sealed semiconductor devices for use as capacitive acceleration sensors or the like having a cap that covers a sensor element formed on a surface of a semiconductor substrate with a gap defined therebetween.
2. Description of the Related Art
In a surface type capacitive acceleration sensor, a sensor element placed on an acceleration sensor wafer segment is covered with a cap wafer segment. In manufacturing such acceleration sensors, a cap wafer is bonded to a plurality of sensor elements before it is cut into a plurality of cap wafer segments.
FIGS. 8
to
11
schematically depict a conventional capacitive acceleration sensor.
FIGS. 8 and 9
depict an acceleration sensor wafer
1
and a plurality of acceleration sensor elements
3
, respectively. The acceleration sensor wafer
1
has an area
2
indicated by hatching, on which a number of acceleration sensor elements
3
are placed and bonded.
FIG. 9
particularly depicts nine acceleration sensor elements
3
juxtaposed with one another and each having a plurality of (for example, five) electrode portions
4
disposed in a line for taking out electric signals.
FIG. 10
depicts a cap wafer
5
that is to be bonded to the acceleration sensor wafer
3
and has a number of elongated openings
6
defined therein and extending in the same direction with a silicon strip
7
interposed between neighboring elongated openings
6
. During the manufacture of the acceleration sensors, the cap wafer
5
is processed separately from the acceleration sensor wafer
1
, and is then placed on and bonded to the acceleration sensor elements
3
.
As shown in
FIG. 11
, when the cap wafer
5
is placed on the acceleration sensor elements
3
, the electrode portions
4
need respective gaps for the purpose of taking out electric signals, and the elongated openings
6
are used for such gaps. Furthermore, because the number of acceleration sensor elements
3
are arranged orderly, the electrode portions
4
form a plurality of rows spaced at regular intervals. For this reason, the elongated openings
6
formed in the cap wafer
5
extend in the same direction at the same intervals as those of the rows of electrode portions
4
.
Accordingly, the relatively narrow elongated openings
6
and the relatively narrow silicon strips
7
are formed alternately in the cap wafer
5
and, hence, a problem arose that the cap wafer
5
is susceptible to cracking during the manufacture thereof. Also, because the bonding is carried out at a high temperature (about 450° C.), the silicon strips
7
are apt to become deformed by heating during the bonding, resulting in insufficient bonding.
SUMMARY OF THE INVENTION
The present invention has been developed to overcome the above-described disadvantages.
It is accordingly an objective of the present invention to provide a method of manufacturing semiconductor devices capable of enhancing the characteristic accuracy by enhancing the reliability and strength during the bonding.
Another objective of the present invention is to provide a method of manufacturing semiconductor devices capable of reducing the size and cost thereof.
In accomplishing the above and other objectives, the method according to the present invention is characterized by forming a plurality of generally rectangular openings into a matrix pattern in a cap silicon wafer so that the plurality of generally rectangular openings are separated by a plurality of row segments extending in a first direction and a plurality of column segments extending in a second direction perpendicular to the first direction. On the other hand, a plurality of semiconductor elements each having a plurality of electrode portions are bonded to a semiconductor wafer. Furthermore, after each of the plurality of generally rectangular openings has been aligned with the plurality of electrode portions of at least one of the plurality of semiconductor elements, the cap wafer is bonded to the plurality of semiconductor elements.
Because the row segments are reinforced by the column segments, cracking of the cap wafer is avoided that has been hitherto caused by conveying or handling it during the manufacture thereof. Also, during bonding, the cap wafer is free from any deformation which has been hitherto caused by heating and, in particular, the bonding can be carried out without being affected by, for example, a horizontal torsion that has a serious effect on the relatively narrow silicon strips of the conventional cap wafer. Accordingly, the reliability and strength during the bonding are enhanced, resulting in a semiconductor device having high characteristic accuracy.
It is preferred that after the cap wafer has been bonded to the plurality of semiconductor elements, the plurality of column segments be removed by grinding the cap wafer. By so doing, all the semiconductor elements mounted on the entire semiconductor wafer can be used, making it possible to increase the yield.
Advantageously, the plurality of column segments are aligned with a plurality of dicing lines, and dicing is carried out along the plurality of column segments, resulting in a reduction in size and cost of chips.
In another aspect of the present invention, the method of manufacturing hermetically sealed semiconductor devices is characterized by bonding a plurality of semiconductor elements each having a plurality of electrode portions to a semiconductor wafer, forming a plurality of recesses in a cap wafer, bonding the cap wafer to the plurality of semiconductor elements so that the plurality of electrode portions of each of the plurality of semiconductor elements are accommodated in one of the plurality of recesses, and grinding the cap wafer to remove those portions of the cap wafer that are aligned with the plurality of electrode portions of each of the plurality of semiconductor elements.
This method facilitates the processing of the cap wafer, and because no openings are formed in the cap wafer before the bonding, the cap wafer has an increased strength. Accordingly, the reliability and strength during the bonding are enhanced, resulting in a semiconductor device having high characteristic accuracy.
REFERENCES:
patent: 6035714 (2000-03-01), Yazdi et al.
Nakamura Kunihiro
Yamaguchi Yasuo
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tsai H. Jey
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