Method of manufacturing semiconductor devices

Details Method of manufacturing semiconductor devices Method of manufacturing semiconductor devices

1991-09-26

1994-10-18

Hearn, Brian

Fishing, trapping, and vermin destroying

437 47, 437241, 437918, 148DIG136, H01L 2170

Patent

active

053568257

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a method of manufacturing semiconductor devices and particularly to a method of manufacturing resistors using a polycrystalline semiconductor layer.


BACKGROUND ART

It has been mainly employed, as a resistor for a semiconductor device, a diffusion resistor which uses a diffusion layer formed in a semiconductor substrate as a resistor The diffusion resistor is constituted in such a manner that boron is doped to a surface portion of, for example, an n-type epitaxial layer to form a p+ diffusion region, then electrodes (e.g., Al electrodes and so on) are formed at opposite ends of the diffusion region.
In recent years, a polycrystalline silicon resistor which uses a polycrystalline silicon film as a resistor has been employed. The polycrystalline silicon resistor is constituted in a manner as shown in FIG. 6 that a polycrystalline silicon film 3 including impurities serving as a resistor is formed on a field insulating layer (SiO.sub.2 layer) 2 formed on a major surface of a silicon substrate 1, thereafter an SiO.sub.2 layer 4 is deposited on the entire surface of the polycrystalline silicon film 3 by the chemical vapor deposition (CVD) process, then a pair of Al electrodes (interconnections) 6 are formed on opposite ends of the polycrystalline silicon film 3 through contact holes. Thus constructed polycrystalline silicon resistor 7 has the following features when compared with the above-described diffusion resistor: changes depending on a depletion layer, so-called back bias dependence, since a junction is separated by applying a reverse bias voltage between it and the neighboring semiconductor region, while the polycrystalline silicon resistor 7 does not have such a back bias dependence; depletion layer is changed depending on a voltage applied thereto to thereby change a resistance value, so-called self bias dependence, while the polycrystalline silicon resistor 7 does not have such a self bias dependence; on the orientation of a wafer and by the influence of stress applied thereto in the assembling-process (e.g., in the molding process), while the polycrystalline silicon resistor 7 is not influenced in its resistance value by the orientation of a wafer and little influenced by the stress in the assembling process; and temperature characteristics.
Now, as one of bipolar transistors, there has been proposed a ultra-high speed bipolar transistor which is constructed in a manner that both a base leading-out electrode and an emitter leading-out electrode are formed by a polycrystalline silicon film, then a base region and an emitter region are formed in a self-alignment fashion by diffusing impurities from the polycrystalline silicon film serving as the emitter leading-out electrode. FIG. 8 illustrates an example of methods of manufacturing the ultra-high speed bipolar transistor. As shown in FIG. 8A, on a major surface of a first conductivity type, e.g., p-type silicon substrate 11, a second conductivity type, e.g., n-type collector buried region 12 and a p-type channel stopper region 13 are formed, then an n-type epitaxial layer 14 is grown thereon. Thereafter, a highly-doped n-type collector leading-out region 15 reaching to the collector buried region 12 is formed, and a field insulating film 16 is formed by the local oxidation on the regions except for the collector leading-out region 15 and a region 14A on which base and collector regions are formed in the succeeding processes. Then, a thin insulating layer, e.g., SiO.sub.2 layer 17 is formed on an entire surface thereof, and a portion thereof corresponding to the region 14A is opened to form a first polycrystalline silicon layer 18 serving as a base leading-out electrode by the CVD process, then boron acting as p-type impurities is doped to the polycrystalline silicon film 18. Thereafter, the p+ polycrystalline silicon film 18 is subjected to the patterning process by a first resist mask 19 having a pattern corresponding to the external configuration of the base leading-out electrode.
Referring to FIG.

REFERENCES:
patent: 4916507 (1990-04-01), Boudou et al.

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