Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-11-26
2004-11-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000
Reexamination Certificate
active
06818527
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a planarization of a semiconductor device structure with a shallow trench isolation (Hereinafter STI).
STI has been used as one device isolation technology for isolating device regions from one another. The STI is aimed at defining trenches in a semiconductor substrate and embedding an insulating material therein to thereby form device isolation layers. After the formation of the device isolation layers by the STI, the resultant product is planarized by CMP (Chemical-Mechanical Polishing) or the like. Such planarization is required to accurately fix up the position of other conductor layers where other conductor layers are further formed on each device isolation layer by photolithography.
A conventional method for carrying out the above processing will be explained below. A silicon nitride film (which will serve as a stopper layer upon CMP) is first formed on a semiconductor substrate, e.g., a silicon substrate. An unillustrated photomask is formed thereon. With the photomask as a mask, the nitride film and the silicon substrate are etched to form trenches (device isolation trenches). Next, a photoresist is removed and a device isolation oxide film is formed within the trenches and on the nitride film. Thereafter, the resultant product is planarized by CMP. Next, the nitride film is removed, thus resulting in the completion of an STI structure.
In the conventional method referred to above, when the trenches are buried with the oxide film, the thickness of the oxide film is set so as to become larger than the sum of the depth of each trench and the thickness of the nitride film. In other words, the upper surface of the oxide film is set so as to be located above the upper surface of the nitride film in a portion of each trench. Thereafter, the oxide film on the nitride film is chipped or cut off by the following CMP, and polishing is stopped when the nitride film is exposed over the whole surface.
The speed of polishing by such CMP as described above depends on each pattern. Namely, a problem arises in that a low-density section (nondense pattern section) of each device region is greater in polishing speed than a high-density section (dense pattern section) of the device region, and the upper surface of the oxide film differs in height in the nondense pattern section and the dense pattern section upon CMP completion.
As countermeasures against such a problem, there has heretofore been adopted a method of inserting a dummy pattern into the low-density section, and effecting photolithography and etching on the high-density section in reverse by use of a device reverse mask to perform a decrease in pattern density or the like, thereby reducing a nondense/dense difference between patterns. However, a wiring rule has recently been further brought into micro form, and there may be cases in which the difference in density between device patterns becomes large according to the property of each formed circuit. The above-described method encounters difficulties in solving the nondense/dense difference. Thus, a problem that the height of the upper surface of the oxide film varies, is becoming increasingly serious.
SUMMARY OF THE INVENTION
The present invention has been made to solve the foregoing problems. It is an object of the present invention to reduce variations in the height of an upper surface of an oxide film in an STI structure, i.e., improve flatness thereof.
In a method of manufacturing a semiconductor device of the present invention, a semiconductor substrate having device regions and an isolation region for separating the device region is provided. Then, a trench is formed in the isolation region of the semiconductor substrate. A nitride film is formed on the device regions of the semiconductor substrate. Next, an oxide film is formed within the trench and on the nitride film so that an upper surface of the oxide film within the trench is located more than about 500 Å below an upper surface of the nitride film. Finally, the oxide film is polished by CMP method so that a height of the upper surface of the oxide film within the trench portion is maintained at less than a height of the upper surface of the nitride film adjacent thereto.
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Japanese Office Action with translation, Patent Application 2002-161352, Oct. 23, 2003.
Japanese Office Action with translation, Ref No MA001387, Jul. 22, 2003, Re Appn. No. 2002/161352.
Fourson George
Rabin & Berdo P.C.
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