Fishing – trapping – and vermin destroying
Patent
1992-02-24
1993-07-20
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 60, 437978, 257295, 257324, H01L 2176, H01L 29788
Patent
active
052293092
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a memory, and in particular, to an electrically rewritable non-volatile memory having a ferroelectric material as capacitor dielectric.
BACKGROUND OF THE INVENTION
In a conventional semiconductor non-volatile memory, use is commonly made of an MIS-type transistor having a phenomenon that the surface potential of a silicon substrate is modulated by injecting a load from the silicon substrate into a trap in an insulating gate or a floating gate. The MIS-type transistor is used similarly in an EPROM (ultraviolet ray erasable non-volatile memory), EEPROM (electrically rewritable non-volatile memory), and the like.
However, such non-volatile memories have disadvantages such as a high information rewriting voltage, typically between 12 and 20 volts, and very long rewriting time (for example, several ten msec in the case of an EEPROM). Moreover, the information rewriting number is limited to 100 to 10,000 times which is a problem when the memory is used repeatedly. In a non-volatile memory having a ferroelectric material which can electrically inverse polarization, write-in time and read-out time are substantially the same in principle, and polarization is maintained even if power is cut off, so that this non-volatile memory has an ideal.
With respect to a non-volatile memory having a ferroelectric material, U.S. Pat. No. 4,149,302 discloses a structure integrating a capacitor consisting of a ferroelectric material on a silicon substrate, and U.S. Pat. No. 3,832,700 discloses a non-volatile memory wherein a ferroelectric film is on the gate portion of a MIS-type transistor.
Moreover, in IEDM '87, pp. 850-851, a non-volatile memory having a structure laminated in a MOS-type semiconductor device such as shown in FIG. 2 was disclosed. In FIG. 2, a P-type Si substrate 201, an element separating LOCOS oxide film 202, an N-type diffusion layer 203, such as a source region, and an N-type diffusion layer 204, such as a drain region, are shown. A gate electrode 205, and an interlayer insulating film 206 are also shown. A ferroelectric film 207 when sandwiched between a lower electrode 208 and an upper electrode 209 results in the formation of a capacitor. A second interlayer insulating film has reference numeral 210 and a wiring electrode 211 is comprised of Al. Such structure of laminating on the upper portion of an MOS-type semiconductor device should distribute wires between the electrode of a ferroelectric film and the high concentration diffusion layer, such as source and drain regions on the semiconductor substrate with the use of Al or other conventional interconnect materials.
One problem with the prior art, as shown in FIG. 2 of the present application, is the large amount of area occupied by the transistor and ferroelectric capacitor regions.
Therefore, the object of the present invention is to solve this problem and aims to provide a semiconductor device, particularly a non-volatile memory, having a small memory cell area even with the use of a ferroelectric film, and has a low cost, and fast information rewriting times.
SUMMARY OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device integrating a ferroelectric film via electrodes by sandwiching the ferroelectric film on the same semiconductor substrate as that where an active element is formed. The method comprises the steps of forming a polysilicon film between a lower electrode and a high concentration diffusion layer and sandwiching a ferroelectric film between the top and bottom electrodes, forming the lower electrode on said polysilicon film, etching said lower electrode and a part of said polysilicon film using etching which has a low selection ratio, and etching the remaining polysilicon film using etching which has a high selection ratio with silicon oxide.
BRIEF DESCRIPTION OF THE DRAWINGS
In describing the preferred embodiment, reference is made to the accompanying drawings wherein:
FIGS. 1(a)-(c) are cross-sectional
REFERENCES:
patent: 4149302 (1979-04-01), Cook
patent: 4437139 (1984-03-01), Howard
patent: 4888630 (1989-12-01), Paterson
patent: 5024964 (1991-06-01), Rohrer et al.
patent: 5046043 (1991-09-01), Miller et al.
Chaudhari C.
Hearn Brian E.
Manzo Edward D.
Murphy Mark J.
Ramtron International Corporation
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