Method of manufacturing semiconductor device provided with capac

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437918, 437919, 437 47, 437200, 148DIG136, H01L 2170

Patent

active

053568265

ABSTRACT:
A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.

REFERENCES:
patent: 3864817 (1975-02-01), Lapham, Jr. et al.
patent: 3988824 (1976-11-01), Bodway
patent: 4367580 (1983-01-01), Guterman
patent: 4609568 (1986-09-01), Koh et al.
patent: 4971924 (1990-11-01), Tigelaar et al.
patent: 5013677 (1991-05-01), Hozumi
patent: 5013678 (1991-05-01), Winnerl et al.
patent: 5120572 (1992-06-01), Kumar
patent: 5126279 (1992-06-01), Roberts
patent: 5187122 (1993-02-01), Bonis
Slater, David B., et al., "Low-Voltage Coefficient Capacitors for VLSI Processes", IEEE Journal of Solid-State Circuits, vol. 24 No. 1, Feb. 1989, pp. 165-173.
Fattaruso, John W., et al, "The Effect of Dielectric Relaxation on Charge-Redistribution A/D Converters", IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1550-1560.
Faraone, Lorenzo, et al, "Characterization of Thermally Oxidized n.sup.+ Polycrystalline Silicon", IEEE Transactions on Electron Devices, vol. ED-32, No. 3, Mar. 1985, pp. 577-583.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing semiconductor device provided with capac does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing semiconductor device provided with capac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device provided with capac will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2371950

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.