Method of manufacturing semiconductor device package

Details Method of manufacturing semiconductor device package Method of manufacturing semiconductor device package

2002-12-26

2004-05-04

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S124000, C438S127000

Reexamination Certificate

active

06730539

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device package, and more particularly to a method of manufacturing a semiconductor device package, in which an electrode surface is formed on a conductive layer of a conductive substrate, thereby miniaturizing the semiconductor device package and simplifying its manufacturing process.
2. Description of the Related Art
Generally, semiconductor devices such as diodes are packaged and these packaged devices are then mounted on a printed circuit board. Structurally, this package easily connects terminals of the semiconductor device to corresponding signal patterns of the printed circuit board and serves to protect the semiconductor device from external stresses, thereby improving reliability of the package.
In order to satisfy recent trends toward miniaturization of semiconductor products, the semiconductor chip packages have also been miniaturized. Therefore, a chip scale package (also referred to as a “Chip Size Package”) has been introduced.
FIG. 1
is a schematic cross-sectional view of a conventional chip scale package. The structure of the chip scale package
10
of
FIG. 1
employs a ceramic substrate
1
and is a diode package with two terminals.
With reference to
FIG. 1
, two via holes, i.e., a first via hole
2
a
and a second via hole
2
b
, are formed on the ceramic substrate
1
. The first and the second via holes
2
a
and
2
b
are filled with conductive material so as to electrically connect the upper surface of the substrate
1
to the lower surface of the substrate
1
. Then, a first and a second upper conductive lands
3
a
and
3
b
are formed on the upper surfaces of the first and the second via holes
2
a
and
2
b
, respectively. A first and a second lower conductive lands
4
a
and
4
b
are formed on the lower surfaces of the first and the second via holes
2
a
and
2
b
, respectively. The second upper conductive land
3
b
is directly connected to a terminal formed on the lower surface of the diode
5
, i.e., a mounting surface of the diode
5
on a printed circuit board, and the first upper conductive land
3
a
is connected to the other terminal formed on the upper surface of the diode
5
by a wire
7
. A molding part
9
using conventional resin is formed on the upper surface of the ceramic substrate
1
including the diode
5
in order to protect the diode
5
from external stresses. Thereby, the manufacture of the package
10
is completed.
The manufactured diode package
10
is mounted on a printed circuit board by a reflow soldering. That is, the diode package
10
is mounted on the printed circuit board by arranging the lower conductive lands
4
a
and
4
b
of the package
10
on each of corresponding signal patterns of the printed circuit board and by then connecting the lower conductive lands
4
a
and
4
b
to the signal patterns of the printed circuit board by the soldering.
As shown in
FIG. 1
, the conventional semiconductor device package usually employs the ceramic substrate. The ceramic substrate is high-priced, thereby increasing the production cost of the semiconductor device package. Further, the via holes of the ceramic substrate are formed by perforating the ceramic substrate by a machine work, thereby imposing a limit in miniaturizing the diameter of the via holes. Therefore, an area as large as the total areas of the via holes is further required. Since the substrate has a large size so as to satisfy the aforementioned conditions, the size of the substrate imposes a limit in miniaturizing the package.
The upper conductive lands, which are encapsulated by the resin molding part, are hexahedral. In this case, gaps are easily generated in an interface between each angle of the upper conductive land and the resin molding part. External dust or moisture is infiltrated into the semiconductor device package through the gaps, thereby deteriorating the reliability of the semiconductor device package. Sometimes, these gaps may cause more serious problems of the package according to the great difference of coefficient of thermal expansion between a resin composite of the resin molding part and a metal material of the upper conductive lands.
Accordingly, a chip scale package, which can solve the aforementioned problems without the ceramic substrate, simplify its manufacturing process and improve its reliability, and a method of manufacturing the chip scale package, have been demanded.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device package, in which almost hemispherical metal bumps are formed on an upper surface of a conductive substrate, thereby improving the reliability of the semiconductor device package.
It is another object of the present invention to provide a method of manufacturing a semiconductor device package, in which successive plating steps are collectively performed at once, thereby simplifying the manufacturing process.
In accordance with the present invention, the above and other objects can be accomplished by the provision of a method of manufacturing a semiconductor device package with a plurality of connection bumps. The method comprises the steps of preparing a conductive substrate, forming a patterned photoresist film with windows for exposing a plurality of connection bump areas on the conductive substrate, forming metal plating layers on the connection bumps area using the photoresist film, forming first gold plating layers on the metal plating layers, forming a plurality of connection bumps on the first gold plating layers, each of the connection bumps having an upper part in an almost hemispherical shape, forming second gold plating layers on the upper surfaces of the connection bumps, removing the photoresist film, and mounting a semiconductor device on the conductive substrate so that terminals of the semiconductor device are electrically connected to each of the connection bumps of the conductive substrate, forming a resin molding part on the upper surface of the conductive substrate including the semiconductor device, and exposing the first gold plating layers by removing the conductive substrate and the metal plating layers.
The present invention may be variously modified according to the alignment of the terminals of the semiconductor device. That is, in accordance with one aspect of the present invention, in case that the semiconductor device has a terminal on its one surface and a terminal on it's other opposing surface, the connection bump areas are two in number and the connection bumps are two in number. Further, in this case, in the step of mounting the semiconductor device on the conductive substrate, the semiconductor device is mounted on the conductive substrate so that one terminal of the semiconductor device is directly connected to one connection bump, and then the other terminal of the semiconductor device is connected to the other connection bump by a wire.
In accordance with another aspect of the present invention, in case that the semiconductor device has a plurality of terminals on its one surface, a plurality of connection bumps are formed on the conductive substrate according to the alignment of the terminals of the semiconductor device. The terminals of the semiconductor device are directly mounted on each of the connection bumps of the conductive substrate.
Preferably, the conductive substrate may be made of copper (Cu) with an excellent etching rate.
Further, preferably, the metal plating layers may be made of nickel (Ni), and the connection bumps may be made of nickel (Ni). Particularly, the metal plating layers are interposed between the first gold plating layers and the conductive substrate, and prevent the diffusion of the first gold plating layers into the conductive substrate, thereby providing an excellent electrical and mechanical interconnection in mounting the semiconductor device packag

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