Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-04-10
2004-10-19
Chaudhari, Chandra (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S797000
Reexamination Certificate
active
06806549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and to a semiconductor device manufactured thereby and, more particularly, to an element isolation technique.
2. Description of the Background Art
Recent progress has been made in miniaturization, packing density, and operating speed of a semiconductor device. In connection with this achievement, decreasing the resistance of a contact hole of high aspect ratio and decreasing a leakage current developing in an element isolation dielectric film have become very important.
A conventional semiconductor device will now be described hereinbelow.
FIG. 43
is a cross-sectional view for describing a circuit section of a conventional semiconductor device.
FIGS. 44A and 44B
are views for describing a mark section of a conventional semiconductor device.
FIG. 43
shows a circuit section of the semiconductor device, wherein a contact hole is opened so as to partial lie off an active region.
In
FIG. 43
, reference numeral
101
designates a silicon substrate;
102
designates an element isolation dielectric film;
103
designates a gate dielectric film;
104
designates a first interconnection layer (gate electrode);
104
a
designates apolysilicon film;
104
b
designates a tungsten film;
105
designates a dielectric film;
106
designates a lightly-doped diffusion layer (a lightly-doped n
−
layer);
107
designates a sidewall;
108
designates a heavily-doped diffusion layer (a heavily-doped n
+
layer);
109
designates an interlayer dielectric film;
120
designates a contact hole;
121
designates a contact (contact plug);
121
a
designates a barrier metal layer;
121
b
designates a tungsten plug;
122
designates a second interconnection layer;
122
a
designates a barrier metal layer; and
122
b
designates a tungsten film.
FIGS. 44A and 44B
show a mark section of the semiconductor device after a resist pattern
123
has been formed for introducing n-type dopants into the polysilicon film
104
a
. Here, the mark section refers to an area in which there is formed an alignment mark to be used for positioning (alignment) a photomask immediately before a pattern is exposed, or an area where there is formed an overlay mark for checking an overlay between an exposure pattern (resist pattern) and a base layer. In relation to
FIG. 44
, those elements which are the same as those shown in
FIG. 43
are assigned the same reference numerals, and repeated explanations thereof are simplified or omitted. Reference numeral
123
shown in
FIG. 44
designates a resist pattern.
The element isolation dielectric film
102
formed in the mark section has hitherto been used as an overlay mark for use with the resist pattern
123
.
The above-described conventional semiconductor device involves the following problems.
First, as shown in
FIG. 43
, when the contact hole
120
is formed outside the active region, the contact hole
120
overlaps the element isolation dielectric film
102
. Here, the interlayer dielectric film
109
and the element isolation dielectric film
102
are of silicon oxide film. For this reason, when the contact hole
120
is formed by means of dry etching the interlayer dielectric film
109
, an etch selectivity to the element isolation dielectric film
102
cannot be ensured sufficiently. Accordingly, the element isolation dielectric film
102
is etched in the form of a slit in a boundary between the element isolation region and the active region; that is, a boundary between the element isolation dielectric film
102
and the heavily-doped diffusion layer
108
(see FIG.
43
).
In this case, plasma damage resulting from dry etching remains in the boundary between the element isolation dielectric film
102
and the heavily-doped diffusion layer
108
, thereby resulting in an increase in leakage current. When the element isolation dielectric film
102
has been etched in the form of a slit so as to become deeper than the heavily-doped diffusion layer
108
, a leakage current is increased to a much greater extent.
Even when the barrier metal layer
121
a
is formed within the contact hole
120
by means of sputtering, the barrier metal layer
121
a
cannot be formed uniformly, and the tungsten plug
121
b
cannot be formed on the barrier metal layer
121
a
with superior coverage. As a result, a seam A is formed in a boundary between the element isolation dielectric film
102
and the heavily-doped diffusion layer
108
. In this case, there arises an increase in the resistance of the contact, whereby the reliability of the plug deteriorates.
Second, the position of an overlay mark (i.e., the element isolation dielectric film
102
) cannot be measured with a high degree of accuracy, because the element isolation dielectric film
102
used as the overlay mark is a translucent silicon oxide film and fails to ensure sufficient contrast. Thus, the position of an overlay mark is measured erroneously. Accordingly, an overlay inspection cannot be effected accurately.
As mentioned above, when the position of the element isolation dielectric film
102
has been measured erroneously, circuit elements cannot be formed accurately. For instance, the semiconductor device shown in
FIGS. 44A and 44B
encounters a problem of failure to attain accurate implantation of n-type dopants into the polysilicon film
104
a
. The same also applies to a case where p-type dopants are introduced into the polysilicon film
104
a
. There may arise a problem of both n-type dopants and p-type dopants being introduced into a predetermined area of the polysilicon film
104
a
, or a problem of no dopants being introduced into the predetermined area. This leads to the increase of the resistance of the gate electrode
104
, thereby inducing device failures.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful plasma etching apparatus and to provide a novel and useful plasma etching method.
A more specific object of the present invention is to provide a highly reliable contact and is to measure an inspection mark accurately.
The above object of the present invention is attained by a following method of manufacturing a semiconductor device and a following semiconductor device.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device having a substrate on which are provided a mark section and a circuit section, the circuit section including an element isolation region for isolating an active region, the method comprises the steps of: forming an element isolation trench in the element isolation region and the mark section; forming an element isolation dielectric film in the element isolation trench; forming an etch stopper film so as to cover at least a portion of an edge of the element isolation dielectric film; and forming circuit elements in the circuit section while the etch stopper film formed in the mark section is used as an inspection mark.
According to a second aspect of the present invention, the method of manufacturing a semiconductor device having a substrate on which are provided a mark section and a circuit section, the circuit section including an element isolation region for isolating an active region, the method comprises the steps of: forming an element isolation trench in the element isolation region and the mark section; forming an element isolation dielectric film in the element isolation trench; forming a gate electrode in the active region; forming an impurity diffusion layer in the substrate adjacent to the gate electrode; forming a dielectric film on the entire surface of the substrate after formation of the impurity diffusion layer; forming an etch stopper film which covers an edge of the element isolation dielectric film, by means of etching back the dielectric film; and forming circuit elements in the circuit section while the etch stopper film formed in the mark se
Blum David S.
Chaudhari Chandra
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