Method of manufacturing semiconductor device having trench...

Details Method of manufacturing semiconductor device having trench... Method of manufacturing semiconductor device having trench...

2001-05-23

2002-10-08

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000

Reexamination Certificate

active

06461934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having trench type element isolation regions, and a method of manufacturing the device.
2. Description of the Background Art
In order to control respective elements quite independently during operation of semiconductor integrated circuits without electrical interference therebetween, the semiconductor integrated circuits require element isolation regions formed therein. One of well-known methods for forming element isolation regions is the trench isolation method, to which various improvements have been made.
The trench isolation method is an element isolation method of providing a trench isolation region by forming a trench in a substrate and filling that trench with a filler material. This method causes little bird's beak that is frequently associated with the LOCOS method, a typical method for forming element isolation regions. Thus, it is an indispensable element isolation forming method to achieve higher density of semiconductor integrated circuits.
FIG. 13
is a cross-sectional view of a semiconductor device D
1
formed by an ordinary trench isolation method. The semiconductor device D
1
comprises, in N- and P-wells
316
,
317
formed on the surface of a semiconductor substrate
301
, trench isolation regions
302
and
303
having isolation lengths L
2
and L
1
, respectively; a P-type MOS transistor M
1
consisting of a gate electrode
304
, a gate insulating film
305
, and P
+
source/drain diffusion layers
306
and
307
; a P-type MOS transistor M
2
consisting of a gate electrode
308
, a gate insulating film
309
, and P
+
source/drain diffusion layers
310
and
311
; and an N-type MOS transistor M
3
consisting of a gate electrode
312
, a gate insulating film
313
, and N
+
source/drain diffusion layers
314
and
315
. It is noted that a potential Vnsub is applied to the N-well
316
.
The trench isolation region formed across the boundary between the N-well
316
and the P-well
317
, namely, an well isolation region
303
, must suppress punch-through between the P-well
317
and the P
+
source/drain diffusion layer
311
which is closest to the P-well
317
in the N-well
316
or punch-through between the N-well
316
and the N
+
source/drain diffusion layer
314
which is closest to the N-well
316
in the P-well
317
. When the well isolation region
303
is formed shallower than the wells
316
and
317
as in the semiconductor device D
1
, in order to suppress the punch-through, the isolation length L
1
of the well isolation region
303
must be longer than the isolation length L
2
of the trench isolation region formed between the adjacent P-type MOS transistors M
1
and M
2
in the N-well
316
(i.e., in-well isolation region
302
) to minimize contact between a depletion layer in the vicinity of each well and a depletion layer in the vicinity of each source/drain diffusion layer. The increase in the isolation length L
1
, however, causes a difficulty in reducing circuit area.
On the other hand, if deep trench isolation regions
402
and
403
are formed to establish an electrical isolation between the N-well
316
and the P-well
317
as in a semiconductor device D
2
of
FIG. 14
, the isolation length L
1
can be reduced. In the ordinary process, however, the trench isolation regions
402
and
403
are formed in the same step, so that both regions have the same depth from the surface of the semiconductor substrate
301
. If the in-well isolation region
402
is formed as deep as the well isolation region
403
as shown in
FIG. 14
, the N-well
316
will be divided into an N-well
316
a
having the P-type MOS transistor M
1
and an N-well
316
b
having the P-type MOS transistor M
2
, which are electrically isolated from each other. This creates the need for applying a potential Vnsub separately to the N-wells
316
a
and
316
b
, offering a drawback to the reduction in circuit area.
To resolve the aforementioned problems, there is provided a semiconductor device D
3
shown in
FIG. 15
in which according to the characteristics of regions to be isolated, only a specific isolation region is formed deep. In the semiconductor device D
3
, an in-well isolation region
502
is formed shallower than the N-well
316
, so that both P-type MOS transistors M
1
and M
2
are in contact with the N-well
316
. Thus, applying a potential Vnsub only to a single given portion of the N-well
316
is enough to obtain substrate potentials of those transistors. Further, an well isolation region
503
has a portion formed deeper than the in-well isolation region
502
. That portion establishes an electrical isolation between the N-well
316
and the P-well
317
. Thus, there is no need to increase the isolation length L
1
.
U.S. Pat. No. 5,536,675 and U.S. Pat. No. 5,411,913, for example, show techniques for manufacturing such a semiconductor device. We will describe the outline of these techniques. First, shallow trenches are formed in any place which would require isolation, by using the photolithographic technique. Then, the photolithographic technique is again used to form a deeper trench in any shallow trench that would require a deeper trench structure. Finally, all trenches are filled with a filler material.
These techniques, however, utilize the photolithographic technique two times to form trenches, so that they require at least two photomasks for resist formation, increasing manufacturing cost. In addition, forming a deeper trench in a shallow trench causes a problem of alignment accuracy of the second photomask.
Another method for manufacturing a structure similar to the semiconductor device D
3
of
FIG. 15
is disclosed in Japanese Patent Laid-Open No. 63-144540A. We will explain this method referring to
FIGS. 16
to
20
. First, a mask material
105
such as a silicon nitride film is formed on a semiconductor substrate
101
. The mask material
105
is patterned to form wide and narrow openings. The substrate is then anisotropically etched through the mask material
105
to form trenches
103
a
and
103
b
having the same depth but different isolation lengths La and Lb (La<Lb), respectively, in the semiconductor substrate
101
(FIG.
16
). After removing impurities or defects from the bottom and side surfaces of the trenches
103
a
and
103
b
by appropriate post-treatment such as etching, insulating films
108
a
and
108
b
such as a silicon oxide film are formed to protect the side and bottom surfaces of the trenches
103
a
and
103
b
. Further, an oxidation-resistant film
109
such as a silicon nitride film is deposited to protect the side and bottom surfaces of the trenches
103
a
and
103
b
from polycrystalline silicon to be filled and oxidized in the subsequent steps. Then, a polycrystalline silicon film
107
is deposited over the entire surface to such a thickness that the trench
103
a
is completely filled and the trench
103
b
has an unfilled space in its central portion (FIG.
17
). The surface of the semiconductor substrate
101
is then anisotropically etched vertically. At this time, the polycrystalline silicon film
107
a
fills up the trench
103
a
, and the polycrystalline silicon film
107
b
remains only on the side surface of the trench
103
b
, exposing the oxidation-resistant film
109
at its bottom (FIG.
18
). By heating this state of the semiconductor substrate
101
in an oxidizing atmosphere, the surfaces or the whole of the polycrystalline silicon films
107
a
and
107
b
are turned to be oxide films
110
a
and
110
b
. Then, with the oxide films
110
a
and
110
b
as masks, the oxidation-resistant film
109
, the insulating film
108
b
, and the substrate
101
all at the bottom of the trench
103
b
are further etched to form a deeper bottom portion
103
c
in the trench
103
b
(at this time, the oxidation-resistant film
109
is simultaneously etched and divided into oxidation-resistant films
109
a
and
109
b
). In this fashion, the T-shaped trench
103
b
is

Affiliated with

Also associated with

Rating

Method of manufacturing semiconductor device having trench... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing semiconductor device having trench..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device having trench... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2952047