Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-09-12
2003-08-05
Cuneo, Kamand (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S111000, C438S012000, C438S124000
Reexamination Certificate
active
06602738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having leads, and more particularly, to an improvement in the flatness of leads.
2. Description of the Background Art
FIG. 11
is a view for describing a related-art semiconductor device. In
FIG. 11
, reference numeral
1
designates a frame;
2
designates a package in which a semiconductor element is sealed with resin;
3
designates a lead;
4
designates a tie bar for interconnecting a plurality of leads
3
; and
5
designates a pinch-cutting section connecting a corner section of the package
2
to a framework
11
.
A related-art method of manufacturing a semiconductor device will now be described.
FIG. 12
is a view for describing a related-art method of manufacturing a semiconductor device (i.e., an assembly flow method).
First, a semiconductor element having been diced (step S
41
) is die-bonded to a die pad of the frame
1
(step S
42
).
Next, the semiconductor element and the leads
3
are wire-bonded by means of gold wires (step S
43
).
The semiconductor element is then sealed with molding resin (step S
44
), thereby forming the package
2
.
The package
2
is subjected to heat treatment (i.e., post curing treatment), thereby completing hardening of the molding resin (step S
45
).
The tie bar
4
is cut (tie bar cutting operation) (step S
46
), and the pinch cutting sections
5
are cut (pinch-cutting operation) (step S
47
).
The leads
3
are plated (step S
48
) and subjected to processing (step S
49
).
Upsizing of a package is continually pursued in association with an improvement in functions of the package, an increase in the number of pins, an increase in the number of rows, and a decrease in thickness of the package, and there exists a demand for making leads of a package flat. Flatness of leads is strongly demanded for improving packing yields of, particularly, a thin quad flat package (TQFP)/low-profile quad flat package (LQFP).
However, the related-art manufacturing method suffers from a problem of flatness failure arising at a rate as high as 1 to 3% after completion of the lead processing operation (step S
49
). Particularly, there may sometimes arise a case where lead flatness failure arises sporadically at a rate up to 30% in a large-sized package such as a TQFP/LQFP.
A warped section A arising in a package after completion of post curing of a mold (step S
45
), as shown in
FIG. 13
, is one reason for occurrence of such a flatness failure. The warpage arises as a result of free expansion of the package
2
for reasons of a difference in coefficient of heat expansion between molding resin and frame material when the hot package
2
is cooled to room temperature after post curing of mold.
FIG. 14
is a graph showing a relationship between warpage of a package and the flatness of leads. As shown in
FIG. 14
, as the degree of warpage of a package increases, the flatness of leads deteriorates. In order to improve the flatness of leads, the warpage of a package must be reduced.
FIG. 15
is a graph showing a relationship between occurrence of warpage and the size of a package. As shown in
FIG. 15
, when one side of the package assumes a length of 14 mm or more, warpage assumes a maximum value of 100 &mgr;m or more. When one side of the package assumes a length of 14 mm or more, warpage increases abruptly, and the flatness of leads deteriorates. Therefore, a mounting yield of a semiconductor device deteriorates.
As mentioned, in the case of a large-sized package having a length per side of 14 mm or more, warpage of the package must be reduced.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device.
A more specific object of the present invention is to provide a semiconductor device having superior lead flatness, by means of diminishing warpage of a package.
The above object of the present invention is attained by a following method of manufacturing a semiconductor device.
According to an aspect of the present invention, in the method of manufacturing a semiconductor device, a semiconductor element is first fixed on a frame. The semiconductor element is connected with a plurality of leads. The semiconductor element is sealed with molding resin, to thereby fabricate a package having a length per side of 14 mm or more. Tie bars interconnecting the plurality of leads are cut. The package is subjected to heat treatment at a predetermined temperature after cutting of the tie bars. Accordingly, warpage of the package can be reduced.
REFERENCES:
patent: 5776798 (1998-07-01), Quan et al.
patent: 6194247 (2001-02-01), Burns et al.
patent: 6399423 (2002-06-01), Matsuura et al.
patent: 5-206177 (1993-08-01), None
patent: 8-250523 (1996-09-01), None
Moriga Namiki
Qin Zhikang
Cuneo Kamand
Mitsubishi Denki & Kabushiki Kaisha
Zarneke David A.
LandOfFree
Method of manufacturing semiconductor device having tie bars... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device having tie bars..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device having tie bars... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3108642