Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-05-31
2011-05-31
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S197000, C438S424000, C257S374000, C257S506000
Reexamination Certificate
active
07951686
ABSTRACT:
A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.
REFERENCES:
patent: 5250836 (1993-10-01), Miura et al.
patent: 5872401 (1999-02-01), Huff et al.
patent: 5969393 (1999-10-01), Noguchi
patent: 7029989 (2006-04-01), Kim
patent: 7214982 (2007-05-01), Kumura et al.
patent: 7355262 (2008-04-01), Ko
patent: 2005/0127474 (2005-06-01), Matsuda
patent: 2006/0030110 (2006-02-01), Kumura
patent: 2006/0220142 (2006-10-01), Tamura
patent: 2006/0228867 (2006-10-01), Mehrotra et al.
patent: 2007/0020879 (2007-01-01), Baek
patent: 2007/0020954 (2007-01-01), Nomaguchi et al.
patent: 2007/0287260 (2007-12-01), Wu et al.
patent: 2004-311954 (2004-11-01), None
Y. Kumagai et al.,Evaluation of Change in Drain Current Due to Strain in 0.13 Micrometer Node MOSFETS, Extended Abstract of the 2002 International Conference on SSDM, pp. 14-15.
USPTO, Notice of Allowance and Notice of Allowability, Dec. 14, 2009, in parent U.S. Appl. No. 11/541,782 [now USP 7,701,106].
USPTO, Final Rejection, Nov. 3, 2009, in parent U.S. Appl. No. 11/541,782 [now USP 7,701,106].
USPTO, Non-Final Rejection, Jun. 10, 2009, in parent U.S. Appl. No. 11/541,782 [now USP 7,701,106].
USPTO, Non-Final Rejection, Oct. 9, 2008, in parent U.S. Appl. No. 11/541,782 [now USP 7,701,106].
USPTO, Restriction Requirement, Jul. 1, 2008, in parent U.S. Appl. No. 11/541,782 [now USP 7,701,106].
Kishii Sadahiro
Satoh Shigeo
Suzuki Kaina
Tanabe Ryo
Terahara Masanori
Dang Phuc T
Fujitsu Limited
Fujitsu Patent Center
LandOfFree
Method of manufacturing semiconductor device having device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device having device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device having device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2689749