Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2001-06-28
2003-07-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
Reexamination Certificate
active
06599809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of manufacturing the same and particularly to semiconductor devices having a marking recess for example for an alignment mark and methods of manufacturing the same.
2. Description of the Background Art
Conventionally, dynamic random access memories (DRAMs) and similar semiconductor devices have an alignment mark, a process management pattern and the like formed for photolithography. Such a mark, a pattern and the like are formed on a semiconductor substrate at a region other than an element formation region provided with a field effect transistor, a capacitor and other similar elements, i.e., an external region.
FIGS. 22 and 23
are schematic cross sections for illustrating a method of conventionally manufacturing a semiconductor device, showing a step of loading a tungsten film into a contact hole of an element formation region, with an alignment mark or trench formed in an external region. With reference to
FIGS. 22 and 23
a method of conventionally manufacturing a semiconductor device will now be described.
Initially, as shown in
FIG. 22
, in the element formation region on a semiconductor substrate (not shown) an interconnection
107
is formed and thereon an interlayer insulating film
101
is formed. In interlayer insulating film
101
a contact hole
103
is formed to reach interconnection
107
. Furthermore, in an external region or a region other than the element formation region, interlayer insulating film
101
has a marking recess
102
serving as an alignment mark. Marking recess
102
has a width W
2
of approximately 1 to 7 &mgr;m, which is sufficiently greater than a width W
1
of contact hole
103
. Then, a barrier metal film
104
is provided to extend from an interior of contact hole
103
to an upper surface of interlayer insulating film
101
. Barrier metal film
104
can be formed of a titanium nitride (TiN) film and a titanium (Ti) film provided in layers. Barrier metal film
104
is also provided simultaneously in marking recess
102
of the external region.
Then a tungsten film
105
having a thickness W
3
is provided on barrier metal film
104
to fill contact hole
103
. Since width W
2
of marking recess
102
is much greater than width W
1
of contact hole
103
, marking recess
102
still has an opening reflecting the geometry of marking recess
102
even after tungsten film
105
is provided. That is, marking recess
102
would never be filled by tungsten film
105
. If marking recess
102
serving as an alignment mark is filled with tungsten film
105
then it would not be employed as the alignment mark. As such, tungsten film
105
has a thickness set not to completely fill marking recess
102
.
Then a chemical mechanical polishing (CMP) process is employed to remove tungsten film
105
and barrier metal film
104
located on the upper surface of interlayer insulating film
101
, to provide a structure as shown in FIG.
23
. As shown in the figure, the external region is provided with a pattern
108
for a region external to a chip, formed of marking recess
102
, a barrier metal film
104
a
and a tungsten film
105
a
to serve as an alignment mark, and the element formation region is provided with a structure
109
therein formed of interconnection
107
and barrier metal and tungsten films
104
b
and
105
b
filling contact hole
103
.
Then, a film deposition process for forming a structure such as an interconnection positioned on interlayer insulating film
101
, a photolithography process employing marking recess
102
as an alignment mark, and other processes are performed to obtain a predetermined semiconductor device.
The above conventional method of manufacturing a semiconductor device, however, is disadvantageous, as described below:
When tungsten film
105
and barrier metal film
104
are chemically mechanically polished on the upper surface of interlayer insulating film
101
and thus removed therefrom, the slurry used in the CMP process is introduced into marking recess
102
. Some of such slurry introduced into marking recess
102
can still remain therein even after it has undergone a washing step following the chemically mechanically polishing process. Consequently, as shown in
FIG. 24
, residual slurry
120
still exists in marking recess
102
. Such residual slurry
120
causes a defect of a structure such as an interconnection formed in a subsequent step and hence a defect of the semiconductor device. Note that
FIG. 24
is a schematic cross section for illustrating a disadvantage of a conventional semiconductor device.
Furthermore, with reference to
FIG. 24
, a conventional semiconductor device can have marking recess
102
having a bottom corner excessively etched and thus recessed to form a so-called subtrench
116
. If such subtrench
116
is formed then in providing a structure in an overlying layer when the alignment mark corresponding to marking recess
102
is used to align a mask or the like the alignment mark's position can be detected erroneously. Consequently, the structure formed in the overlying layer is offset from a predetermined position (or a structural defect occurs). Such a structural defect results in an operational defect of the semiconductor device and thus reduces the yield thereof.
FIGS. 25 and 26
are schematic cross sections for illustrating another disadvantage of a conventional semiconductor device. As shown in the figures, an external region is provided with a marking recess
119
serving as a pattern for a region external to a chip and having a greater width. As shown in the figures, the semiconductor device is basically similar in structure to the
FIG. 23
semiconductor device except that marking recess
119
is greater in width than the
FIG. 23
marking recess
102
. In the
FIGS. 25 and 26
semiconductor devices, marking recess
119
is used as a checking pattern further greater in width than an alignment mark, such as a film-thickness monitoring pattern.
With reference to
FIG. 25
, interlayer insulating film
101
is provided with marking recess
119
and contact hole
103
and then, as shown in
FIG. 22
, barrier metal film
104
(
FIG. 22
) and tungsten film
105
(
FIG. 22
) are provided. Then, barrier metal film
104
and tungsten film
105
are chemically mechanically polished on an upper surface of interlayer insulating film
101
and thus removed therefrom, when, with marking recess
119
having a large width, an abraser pad being used in the chemically mechanically polishing process contacts tungsten film
105
and barrier metal film
104
located on a bottom surface of marking recess
119
and as a result, as shown in
FIG. 25
, marking recess
119
would have a bottom portion with tungsten film
105
a
, barrier metal film
104
a
and interlayer insulating film
101
abrased and thus removed, as labeled
121
.
Furthermore, as shown in
FIG. 26
, the chemically mechanically polishing process can result in marking recess
119
having an upper portion with tungsten film
105
a
and barrier metal film
104
a
abrased and thus removed, as labeled
122
.
Marking recess
119
having its internal tungsten film
105
a
and barrier metal film
104
excessively removed can no longer be used as a film-thickness monitoring pattern. As a result, the film thickness cannot be controlled with high precision, also resulting in a reduction of the product yield.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor device capable of preventing yield reduction and a method of manufacturing the same.
The present invention in one aspect provides a method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, including the steps of: providing in the external region an interlayer insulating film having a marking recess; providing a covering film extending from an internal
Anma Masatoshi
Ooto Kenichi
McDermott & Will & Emery
Tsai Jey
LandOfFree
Method of manufacturing semiconductor device having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor device having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor device having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3057898