Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-07-10
2004-01-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S143000, C438S150000, C438S149000, C438S160000, C438S016000, C438S017000, C356S600000, C356S237200, C250S458100
Reexamination Certificate
active
06673640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of detecting a crystal defect, a method of manufacturing a semiconductor device for evaluation, a method of evaluating a crystal defect and a semiconductor device for evaluation, which are used to evaluate a crystal defect generated within a semiconductor layer.
2. Description of the Background Art
Crystal defects which are likely to occur during manufacture of a semiconductor substrate, or are induced in a semiconductor substrate due to a manufacturing process for a semiconductor device, cause degradation of various device characteristics such as junction characteristics (i.e., increase in junction leakage), on one hand. On the other hand, however, crystal defects, provided that the density or location thereof is controlled, are utilized as gettering sites for removing metals contained in a region where a device is to be formed. For this reason, quantitative evaluation of crystal defects generated within a semiconductor substrate has been conventionally conducted.
As a method of evaluating a crystal defect occurring during manufacture of a semiconductor substrate, a method using a preferential etching process is well known. According to this method, first, crystal defects are detected such that the crystal defects appear in units of microns by performing a preferential etching process using a predetermined etchant. Thereafter, observation of the detected crystal defects is carried out with an optical microscope or a scanning electron microscope, to simply count the crystal defects. For the predetermined etchant, an etchant containing chromium such as Wright etch solution (a liquid mixture of HF, HNO
3
, CrO
3
, Cu(NO
3
), CH
3
COOH and H
2
O), Secco etch solution (a liquid mixture of HF and K
2
Cr
2
O
7
), and Sirtl etch solution (a liquid mixture of HF, CrO
3
and H
2
O), or an etchant not containing chromium such as a liquid mixture of HF and HNO
3
, has been employed.
Semiconductor devices recently employed to practice includes a semiconductor device with an SOI substrate having a structure in which a thin film SOI layer with a film thickness of 100 nm or smaller is formed on a buried oxide layer, and a semiconductor device with a substrate having a structure in which a thin film surface layer (Si layer or SiGe layer) with a film thickness of 100 nm or smaller is formed on a silicon substrate. In evaluating crystal defects generated within the substrates having the aforementioned structures, use of the conventional evaluation method which entails a preferential etching process has caused some problems. For example, it is probable that the thin film SOI layer or the thin film surface layer disappears due to the etching process. Further, microroughness is liable to be caused in a surface of the thin film SOI layer, an interface between the thin film SOI layer and the buried oxide layer, a surface of the thin film surface layer, or an interface between the thin film surface layer and the silicon substrate, which would make it difficult to detect the crystal defects.
The conventional evaluation method has a further disadvantage as follows. That is, the conventional method includes a preferential etching process by which also a wafer is unavoidably etched in detecting crystal defects. Accordingly, the wafer can no longer serve as a product wafer after that. For this reason, the conventional method requires an off-line test which is carried out by picking up a sample wafer for evaluation from a lot of wafers to accomplish evaluation. In other words, according to the conventional method, an in-line test which is performed using a product wafer without removing it from a manufacturing line is impossible.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems. It is therefore an object of the present invention to obtain a method of detecting a crystal defect, a method of manufacturing a semiconductor device for evaluation, a method of evaluating a crystal defect, and a semiconductor device for evaluation, which allow a crystal defect occurring within a thin film SOI layer or a thin film surface layer to be evaluated using an in-line test while avoiding using a preferential etching process.
According to the present invention, the method of manufacturing a semiconductor device for evaluation includes the steps (a) to (d). The step (a) is to prepare a substrate having a semiconductor layer which contains a crystal defect to be evaluated. The step (b) is to form an insulating film on at least an evaluation region of the semiconductor layer. The step (c) is to form a metal-containing film containing a metal on the insulating film. The step (d) is to cause the metal contained in the metal-containing film to pass through the insulating film and diffuse into the semiconductor layer by carrying out a heat treatment, to detect the crystal defect.
The metal diffusing in the semiconductor layer in the step (d) is gettered by the crystal defect in the semiconductor layer. As a result, a metal-semiconductor compound is formed in a portion where the crystal defect has existed, thereby to detect the crystal defect. Accordingly, it is possible to obtain a semiconductor device for evaluation of which crystal defect in the semiconductor layer is satisfactorily detected.
This and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5244819 (1993-09-01), Yue
patent: 6001711 (1999-12-01), Hashimoto
patent: 59-158532 (1984-09-01), None
patent: 11-274257 (1999-10-01), None
S. M. Sze. Physics Of Semiconductor Devices, 1981, John Wiley & Sons, 2 Edition, P158.
Keshavan Belur V
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
Smith Matthew
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