Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-08-03
2003-01-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S463000, C438S689000
Reexamination Certificate
active
06511897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device as well as a reticle and a wafer used therein, in particular to a method of manufacturing a semiconductor device wherein particles caused by cutting of a conductive layer are not scattered at the time of dicing during assembly, a reticle used in the exposure steps of this process and a wafer on which patterning is carried out in such a process.
2. Description of the Background Art
A conventional method of forming a pattern on a wafer by using photolithographic technology is described. A reticle is used in a photolithographic process for transcribing a predetermined pattern to a resist. As shown in
FIG. 29
, a plurality of chip pattern regions
121
are formed in a reticle
120
in order to form chip products.
In addition, dicing line pattern regions
122
are formed in order to partition the plurality of chip pattern regions
121
. Moreover, peripheral dicing line pattern regions
123
and
124
are formed along the outer periphery of the reticle
120
.
In the dicing line pattern regions
122
, a mark for adjusting the alignment or a TEG (Test Element Group), for example, for testing the electrical characteristics are arranged. These dicing line pattern regions
122
and peripheral dicing line pattern regions
123
and
124
allow dicing line regions, which are necessary for cutting off a plurality of chip products, respectively, to be patterned onto a wafer.
The widths of the dicing line regions on the wafer are required to be the widths of several tens of a &mgr;m (for example, approximately 60 &mgr;m) at the minimum, taking into account the dispersion of the width of a cutter blade used for the dicing, the position of the cutter blade at the time of the dicing, or the like.
Here, the widths of the peripheral dicing line pattern regions
123
and
124
are set at the widths of two major types in order to make reduce the ratio (occupying ratio) of the dicing line regions in the wafer plane. In this case, the widths of the peripheral dicing line pattern regions
123
a
and
123
b,
which are positioned around the outer periphery of the adjoining two sides are set at a narrower width than the width of the peripheral dicing line pattern regions
124
a
and
124
b
positioned around the outer periphery of the other adjoining two sides. For example, the width of the peripheral dicing line pattern region
123
a
is several &mgr;m.
Next, exposure steps in the photolithographic process using the above reticle
120
are described. The reticle
120
is mounted in an exposure unit wherein an exposure light irradiates (is shot at) the resist formed on the wafer via the reticle
120
in sequence.
By means of one shot, a pattern corresponding to the reticle
120
is transcribed onto the wafer. Thereby, as shown in
FIG. 30
, the peripheral dicing line pattern region
123
a
part of the reticle
120
becomes a dicing line region
223
a
which has the width Xc. The peripheral dicing line pattern region
123
b
part becomes the dicing line region
223
b
which has the width Yc. The peripheral dicing line pattern region
124
a
part becomes the dicing line region
224
a
which has the width Ya. The peripheral dicing line pattern region
124
b
part becomes the dicing line region
224
b
which has the width Xa. The dicing line pattern region
122
a
part becomes the dicing line region
222
a
which has the width Xb. The dicing line pattern region
122
b
part becomes the dicing line region
222
b
which has the width Yb.
Next, as shown in
FIG. 30
, the next shot is carried out at the position wherein the outer periphery of the dicing line region
224
b,
which corresponds to the peripheral dicing line pattern region
124
b
of the reticle
120
, approximately agrees with the outer periphery of the dicing line region
223
a
resulting from the first shot.
At this time, the width of the peripheral dicing pattern region of the reticle
120
, in particular, is set so that the width gained by combining the width of the dicing line region
223
a,
formed through the first shot, and the width of the dicing line region
224
b,
formed through the next shot, becomes approximately equal to the width Xb.
The same positional relationships are used for the exposure in the next shot and in the shot after that. Here, though in
FIG. 30
only the X direction is shown, the same positional relationships are used for carrying out the exposure in the Y direction. In addition, the peripheral region of the wafer wherein a chip formation region is only partially formed through the first shot does not undergo exposure processing.
In this manner, by irradiating a wafer with an exposure light (by giving a shot of an exposure light to a wafer) in sequence, chip formation regions
102
and dicing line regions are formed in the wafer
101
as shown in FIG.
31
. The conventional exposure steps are carried out in the above manner.
In the above described exposure method using the reticle
120
, however, the problem arises as shown in the following. At the time of transcribing chip patterns onto a wafer, as shown in
FIG. 30
, the next shot is carried out under the positional relationships where the outer periphery of the dicing line region
224
b,
which corresponds to the peripheral dicing line pattern region
124
b
of the reticle
120
, approximately agrees with the outer periphery of the dicing line pattern region
223
a
resulting from the first shot.
Therefore, regions which correspond, only, to the peripheral dicing line pattern region
123
a
are transcribed between, for example, the last chip formation regions
102
a
in the X direction and the wafer peripheral region P as shown in FIG.
31
. The same conditions apply to the last chip formation regions
102
b
in the Y direction.
In addition, as described above, since the entire chip formation region is not formed in the wafer peripheral region P, the resist, which does not undergo exposure processing and is not patterned, remains in the wafer peripheral region P.
In the case that a predetermined etching process is carried out based on such exposure processing, a dicing line region D (
223
a
), which corresponds, only, to the peripheral dicing line pattern region
123
a,
is formed between the chip formation region C (
102
a
) and the wafer peripheral region P, as shown in FIG.
32
.
Then, in the wafer peripheral region P, the film formed in each step is not patterned and remains in the unchanged condition.
As described above, as for the width of a dicing line region, generally the widths of several tens of a &mgr;m is required. As shown in
FIG. 32
, however, the width of the dicing line region D (
223
a
) formed between the chip pattern region C (
102
a
), positioned in the outermost periphery, and the wafer peripheral region P is approximately a few &mgr;m.
The dicing line region D is not formed with the sufficient width required for dicing. Therefore, in the dicing at the time of the actual assembly process as shown by the arrow
116
, the wafer peripheral region P, practically, is diced.
On the other hand, the film formed in each step remains as it is in the wafer peripheral region P. Among these films, conductive films
111
and
113
made of aluminum, for example, for forming wires are included. Therefore, when this wafer peripheral region P is diced, the conductive films
111
and
113
are also diced so that particles, resulting from the cutting of the conductive films
111
and
113
, are generated.
In the case that a wire bonding is carried out in the assembly process under the condition where the particles resulting from the cutting of the conductive films
111
and
113
are included in the system, in some cases wires form an electrical short circuit due to the scattered particles resulting from the cutting of the conductive films
111
and
113
. Therefore, a chip product that is free of defects becomes a defective chip, which becomes a factor leading to a lowering of the yield of the products.
In addition, it also
Arima Satoshi
Kamitani Yoshikazu
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Pham Ly Duy
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