Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1989-01-12

1990-08-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 40, 437 44, 437 47, 437 52, 437229, H01L 21336

Patent

active

049506170

ABSTRACT:
This invention discloses a semiconductor integrated circuit in which an input protecting circuit and an inner circuit are formed on a single semiconductor substrate and a MOS transistor of the inner circuit is formed by mask-alignment. The source and drain regions of the MOS transistor of the input protecting circuit are formed by self-alignment, so that the impurity concentration of the source and drain regions is increased and the diffusion resistance thereof is reduced, thereby increasing the junction breakdown power caused by a drain current. In addition, the radii of curvature of the junction curved surface portions of the source and drain regions of the MOS transistor of the input protecting circuit are increased so as to reduce the electric field intensity at the junction curved surface portions, thereby improving the junction breakdown withstand characteristics.

REFERENCES:
patent: 4070687 (1980-01-01), Ho et al.
patent: 4235011 (1980-11-01), Butler et al.
patent: 4294002 (1981-10-01), Jambotkar et al.
patent: 4354307 (1982-10-01), Vinson et al.
patent: 4375717 (1983-03-01), Tunnel

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