Fishing – trapping – and vermin destroying
Patent
1991-02-12
1993-08-24
Wilczewski, Mary
Fishing, trapping, and vermin destroying
437186, 437233, H01L 2336
Patent
active
052388590
ABSTRACT:
In the selective anisotropic etching by RIE of a first poly-Si film formed on a gate oxide film the poly-Si film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a second poly-Si film, followed by applying RIE. This particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the second poly-Si film and the portion of the first polysilicon film thereunder.
REFERENCES:
patent: 4488351 (1984-12-01), Momose
patent: 4691433 (1987-09-01), Pimbley et al.
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
patent: 4906589 (1990-03-01), Chao
patent: 4951100 (1990-08-01), Parrillo
patent: 4963504 (1990-10-01), Huang
patent: 4971922 (1990-11-01), Watabe et al.
patent: 4978626 (1990-12-01), Poon et al.
patent: 5015599 (1991-05-01), Verhaar
patent: 5061647 (1991-10-01), Roth et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1-Process Technology, Lattice Press, 1986, pp. 556-557.
Huang et al., "A Novel Submicron LDD Transistor With Inverse-T Gate Structure", IEDM 1986, pp. 742-745.
Izawa et al., "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI," IEEE Trans. on Electron Devices, vol. 35, No. 12, Dec. 1988, pp. 2088-2093.
Izawa et al., "The Impact of Gate-Drain Overlapped LDD (GOLD) For Deep Submicron VLSI's", IEDM 1987, pp. 38-41.
Kamijo Hiroyuki
Mikata Yuuichi
Usami Toshiro
Kabushiki Kaisha Toshiba
Wilczewski Mary
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