Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-02-12
2004-10-26
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S723000, C438S724000, C438S740000, C438S743000, C438S744000
Reexamination Certificate
active
06809038
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-207254, filed on Jul. 16, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of dry etching a silicon nitride film selectively, and more particularly to a method of manufacturing a semiconductor device suitable for manufacturing a flash memory.
2. Description of the Prior Art
Referring to
FIGS. 1
to
6
, a conventional method of manufacturing a NOR-type flash memory will be first described.
FIGS. 1A
to
1
C are plan views showing, in the order of steps, an example of the conventional method of manufacturing a flash memory; and
FIGS. 2
to
6
are cross-sectional views similarly showing the method of manufacturing a flash memory in the order of steps. Note that
FIGS. 1A
to
1
C are plan views of a memory cell formation portion. Moreover, note that
FIGS. 2A
,
3
A,
4
A,
5
A and
6
A illustrate cross-sections of a peripheral circuit formation portion and that
FIGS. 2B
,
3
B,
4
B,
5
B and
6
B illustrate cross-sections taken along the line I—I in FIG.
1
A. Moreover, in order to simplify the description, a transverse direction of
FIG. 1A
will be referred to as an X direction and a longitudinal direction thereof will be referred to as a Y direction.
First, as shown in
FIG. 1A
, a plurality of trenches arrayed in the X and Y directions are formed on a semiconductor substrate
50
. Then, an insulator is buried in the trenches, thus forming an element isolation film
51
. Thereafter, as shown in
FIGS. 2A and 2B
, a silicon oxide film
52
is formed by subjecting a surface of the semiconductor substrate
50
to thermal oxidation.
Next, a conductive polysilicon film
53
is formed on an entire upper surface of the semiconductor substrate
50
. Then, the conductive polysilicon film
53
in the memory cell formation portion is patterned, thus forming a plurality of strip-shaped polysilicon films
53
extending in the Y direction as shown in FIG.
1
A. These strip-shaped polysilicon films
53
are formed so as to have both side edge portions thereof in their width direction overlap with edge portions of two element isolation films
51
adjacent to each other, respectively.
Next, an intermediate insulating film
54
is formed over the entire upper surface of the semiconductor substrate
50
. Thereafter, a photoresist film
57
is formed on this intermediate insulating film
54
, and an opening portion is provided in the resist film
57
by executing an exposure/developing process thereto. Accordingly, as shown in
FIG. 2A
, the intermediate insulating film
54
in the peripheral circuit formation portion is exposed.
Thereafter, by use of the resist film
57
as a mask, the intermediate insulating film
54
and the polysilicon film
53
in the peripheral circuit formation portion are sequentially etched and removed. After completing the etching, the resist film
57
is removed.
After removing the intermediate insulating film
54
and the polysilicon film
53
in the peripheral circuit formation portion as described above, as shown in
FIGS. 3A and 3B
, a conductive polysilicon film
58
is formed over the entire upper surface of the semiconductor substrate
50
, and a silicon oxide film
59
and a silicon nitride film
60
are further formed thereon. Thereafter, on the silicon nitride film
60
, a resist film
61
is formed in a predetermined shape. Then, the silicon nitride film
60
, silicon oxide film
59
, polysilicon films
58
and
58
a
, intermediate insulating film
54
and polysilicon film
53
are sequentially etched by use of the resist film
61
as a mask. After completing the etching, the resist film
61
is removed.
By this etching, as shown in
FIGS. 4A and 4B
, a gate electrode
58
b
made of polysilicon is formed in the peripheral circuit formation portion, and a floating gate
53
a
and a control gate
58
a
, which are made of polysilicon, are formed in the memory cell formation portion. As shown in
FIG. 1B
, the control gate
58
a
extends in the X direction, and one floating gate
53
a
is formed for each memory cell.
Next, by use of the silicon nitride film
60
in the memory cell formation portion as a mask, ion implantation of impurities is performed to the surface of the semiconductor substrate
50
via the silicon oxide film
52
. Thus, a source layer
62
s
and a drain layer
62
d
are formed. As shown in
FIG. 1B
, the source layer
62
s
is formed to extend in the X direction, and the drain layer
62
d
is formed in a region surrounded by the element isolation films
51
and control gates
58
a.
Moreover, by use of the silicon nitride film
60
in the peripheral circuit formation portion as a mask, ion implantation of impurities is performed to the surface of the semiconductor substrate
50
via the silicon oxide film
52
. As a result, lightly doped drain (LDD) layers
62
b
are formed on both sides of a gate electrode
58
b
, respectively.
Thereafter, the silicon nitride film
60
is removed by wet etching using thermal phosphoric acid.
Next, a silicon oxide film is formed over the entire upper surface of the semiconductor substrate
50
, and anisotropic etching is carried out thereto. Thus, as shown in
FIGS. 5A and 5B
, sidewalls
63
a
are formed respectively on both sides of each floating gate
53
a
and each control gate
58
a
in the memory cell formation portion, and sidewalls
63
b
are formed respectively on both sides of the gate electrode
58
b
in the peripheral circuit formation portion. Thereafter, by use of the gate electrode
58
b
and the sidewalls
63
b
as a mask, ion implantation of impurities at a high density is executed to the substrate surface in the peripheral circuit formation portion. Thus, on both sides of the gate electrode
58
b
, source/drain layers
64
b
are formed, respectively.
Next, a metal film is formed over the entire upper surface of the semiconductor substrate
50
, and heat treatment is given thereto. Thus, metal atoms in the metal film and silicon atoms of the control gate
58
a
, gate electrode
58
b
and source/drain layer
64
b
are reacted to each other. Accordingly, as shown in
FIGS. 6A and 6B
, silicide films
65
a
,
65
b
and
65
c
are formed. Thereafter, the non-reacted metal film is removed by etching.
As shown in
FIG. 1C
, a silicon oxide film is next formed as an interlayer insulating film
66
over the entire upper surface of the semiconductor substrate
50
. Then, by photolithography, contact holes
66
h
are formed, respectively, which reach to the silicide film
65
c
and the source layer
62
s
from an upper surface of the interlayer insulating film
66
. After that, a metal film is formed over the entire upper surface of the semiconductor substrate
50
, and this metal film is patterned. Thus, bit lines
67
a
extending in the Y direction are formed in the memory cell formation portion, and wirings
67
b
are formed in the peripheral circuit formation portion. The bit lines
67
a
are electrically connected to the drain layers
62
d
in the memory cell formation portion through the contact holes
66
h
, and the wirings
67
b
are electrically connected to the source/drain layers
64
b
in the peripheral circuit formation portion through the contact holes
66
h
and the silicide films
65
c
. In such a manner, a flash memory is completed.
However, the inventor of the present application considers that there are problems described below in the conventional semiconductor device manufacturing method described above.
Normally, in order to prevent a leak of an electric charge from the floating gate
53
a
to the control gate
58
a
, the intermediate insulating film
54
has, as shown in
FIG. 7
, a three-layered structure of a first silicon oxide layer
54
a
, a silicon nitride layer
54
b
and a second silicon oxide layer
54
c.
In the conventional semiconductor device manufacturing method, when t
Fujitsu Limited
Goudreau George A.
Westerman Hattori Daniels & Adrian LLP
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