Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2002-11-26
2004-08-31
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S239000, C438S250000
Reexamination Certificate
active
06784067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and specifically to a method which enhances the reliability of an insulating film of a capacitor and prevents penetration of contact holes through a capacitor electrode.
2. Description of the Related Art
Enhancing the reliability of an insulating film interposed between an upper electrode and a lower electrode of a capacitor is very important to a method of manufacturing a semiconductor device. In a method of manufacturing a semiconductor device including a conventional capacitor structure, a transistor is first formed on a wafer. A metal layer, which provides a lower electrode of a capacitor, and an insulating film for the capacitor, which is formed off an Si oxide film or the like, are deposited over the transistor in this order.
The metal layer (generally called simply “metal” hereafter) and the insulating film are patterned so as to form a lower electrode and dielectric, and a capacitor metal layer (generally called simply “capacitor metal” hereafter) is formed thereon. The capacitor metal is patterned to form an upper electrode. In order to make contact with the lower and upper electrodes, contact holes are fabricated in an interlayer film formed at their upper portions.
In the aforementioned conventional manufacturing method, the lower electrode is first patterned and thereafter the capacitor metal (CM) is deposited and etched to form the upper electrode. However, since a resist is directly applied onto the insulating film upon patterning of the lower electrode in the conventional manufacturing method, the resist is directly applied even to an area interposed between the upper and lower electrodes on the insulating film as a matter of course. Therefore, the film quality of the surface of the insulating film changes and is affected by an organic release agent or the like even upon removing the resist on the insulating film after the etching, thereby deteriorating the reliability of the insulating film.
If an etching-rate selection ratio is low when the contact holes are collectively made open on the lower and upper electrodes by etching, then there is a possibility that the upper electrode will be excessively etched due to the difference between their depths, and the contact holes will be defined through the upper electrode.
Further, when the organic release agent or the like for removing the resist infiltrates into edge portions of the upper electrode upon formation of the lower electrode by etching, this will influence the quality of the insulating film near the edge portions. Furthermore, a problem arises in that when the interlayer film is deposited by CVD or the like using plasma after the formation of the capacitor, the insulating film is damaged by the plasma of CVD and thereby brought into deterioration, whereby the reliability of the insulating film is reduced.
SUMMARY OF THE INVENTION
The present invention may provide a method of manufacturing a semiconductor device having a capacitor, wherein an insulating film is high in reliability.
In a method of manufacturing a capacitor of the present invention, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.
REFERENCES:
patent: 6475860 (2002-11-01), Kwon et al.
patent: 6509593 (2003-01-01), Inoue et al.
patent: 6579753 (2003-06-01), Yamanobe
patent: 10-056063 (1996-05-01), None
patent: 2001-274340 (2001-10-01), None
Japanese Official Notice of Reason for Rejection, dated Aug. 5, 2003.
Le Thao P.
Nelms David
Oki Electric Industry Co, Ltd.
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