Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2001-06-06

2003-08-19

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S592000, C438S294000, C438S303000, C438S664000, C438S683000

Reexamination Certificate

active

06607964

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which dynamic random access memory (DRAM) and logical circuit are arranged.
2. Description of Related Art
FIG. 10
is a sectional view showing the structure of a semiconductor device in which DRAM and logical circuit are arranged. In
FIG. 10
, numeral number
1
indicates a semiconductor device (hereinafter, denoting an embedded DRAM, and called eRAM for short).
2
indicates a memory cell unit of a DRAM,
3
indicates the whole field other than the memory cell unit
2
of the DRAM. In the field
3
other than the memory cell unit
2
of the DRAM, a logical circuit and a peripheral circuit of the DRAM are arranged.
Also,
11
indicates a silicon substrate.
12
indicates a bottom n-type (N) well.
13
indicates each of two p-type (P) wells.
14
indicates each of P wells.
15
indicates each of two N wells.
16
indicates an element isolation oxide film.
17
and
18
respectively indicate N
−
diffusion layers.
19
indicates an N
+
diffusion layer.
20
indicates a P
−
diffusion layer.
21
indicates a P
+
diffusion layer.
22
to
25
respectively indicate gate electrodes formed in two-layer structure. A plurality of insulation films
22
a
to
25
a
are respectively arranged on the gate electrodes
22
to
25
.
26
indicates a first side wall of both the gate electrode
24
and the insulation film
24
a
.
27
indicates a second side wall of both the gate electrode
25
and the insulation film
25
a
.
28
indicates a bit line.
29
indicates a bottom-of-capacitor electrode.
30
indicates a top-of-capacitor electrode.
31
indicates a dielectric film arranged between the bottom-of-capacitor electrode
29
and the top-of-capacitor electrode
30
.
32
to
37
respectively indicate interlayer insulation films.
38
to
41
respectively indicate metallic wires.
42
indicates a contact hole.
43
to
45
respectively indicate via holes.
46
indicates a metallic layer embedded in the contact hole
42
.
47
to
49
respectively indicate metallic layers embedded in the via holes
43
to
45
.
50
indicates a glass coat.
In the memory cell unit
2
of the DRAM shown in
FIG. 10
, only principal elements of the memory cell unit
2
are shown. That is, an n-channel metal oxide semiconductor (NMOS) having the gate electrode
22
and a capacitor which is composed of the bottom-of-capacitor electrode
29
, the top-of-capacitor electrode
30
and the dielectric film
31
connected with the N
−
diffusion layer
17
of the NMOS are shown in
FIG. 10
as principal elements of the memory cell unit
2
of the DRAM. Also, the bit line
28
connected with the N
−
diffusion layer
17
of the NMOS and the gate electrode
23
composing an NMOS of another memory cell are shown in
FIG. 10
as other principal elements of the memory cell unit
2
of the DRAM.
Also, in the field
3
other than the memory cell unit
2
of the DRAM shown in
FIG. 10
, only principal elements of the field
3
are shown in FIG.
10
. That is, as shown in
FIG. 10
, an NMOS having the first side wall spacer
26
and a PMOS having the second side wall spacer
27
are arranged in the field
3
as a logical circuit or a peripheral circuit of the DRAM.
In the logical circuit of a conventional eRAM, to perform high speed operations, a silicide layer (not shown) formed of CoSi
2
or the like is formed on both the N
+
diffusion layer
19
, which has the first side wall spacer
26
and functions as a source/drain diffusion layer of the NMOS, and the P
+
diffusion layer
21
which has the second side wall spacer
27
and functions as a source/drain diffusion layer of the PMOS, to reduce resistance in each of the
+
diffusion layer
19
and the P
+
diffusion layer
21
.
In contrast, in the peripheral circuit of the DRAM of the conventional eRAM, no silicide layer is formed on both the N
+
diffusion layer
19
, which has the first side wall spacer
26
and functions as a source/drain diffusion layer of the NMOS, and the P
+
diffusion layer
21
which has the second side wall spacer
27
and functions as a source/drain diffusion layer of the PMOS. Here, in the peripheral circuit of the DRAM, in addition to a MOS transistor having a wall side spacer, a MOS transistor such as a high withstand-pressure MOS transistor having no side wall spacer exists.
Next, a conventional manufacturing method of the eRAM
1
shown in
FIG. 10
will be described below.
FIG. 11A
,
FIG. 11B
,
FIG. 11C
,
FIG. 12A
,
FIG. 12B
,
FIG. 12C
, FIG.
13
A and
FIG. 13B
are respectively sectional views showing conventional steps of forming the eRAM in the step order. In
FIG. 11A
to
FIG. 13B
, steps of forming the NMOS arranged in the memory cell unit
2
of the DRAM are shown on the left side, and steps of forming both the NMOS with the first side wall spacer
26
and the PMOS with the second side wall spacer
27
, which are arranged in the field
3
other than the memory cell unit
2
of the DRAM, are shown on the right side. However, in the peripheral circuit of the DRAM, no silicide layer is formed on both the N
+
diffusion layer
19
having the first side wall spacer
26
and the P
+
diffusion layer
21
having the second side wall spacer
27
. Therefore, both the NMOS with the first side wall spacer
26
and the PMOS with the second side wall spacer
27
shown on the right side of the
FIG. 12C
, FIG.
13
A and
FIG. 13B
are limited to those arranged in the logical circuit, and the steps of forming a silicide layer are shown in
FIG. 12C
, FIG.
13
A and FIG.
13
B. Here, in
FIG. 11A
to
FIG. 13B
, the bottom N well
12
, the P wells
13
and
14
, the N wells
15
, a gate oxide film, the N
−
diffusion layers
17
and
18
, the N
+
diffusion layer
19
, the P
−
diffusion layer
20
and the P
+
diffusion layer
21
are omitted and not shown.
When eRAM is manufactured according to a conventional method, the bottom N well
12
, the P wells
13
and
14
and the N wells
15
are initially formed in the silicon substrate
11
. Thereafter, the element isolation oxide film
16
is formed in the silicon substrate
11
. Thereafter, a gate oxide film is formed on the silicon substrate
11
. Thereafter, the gate electrodes
22
to
25
, on which the insulation films
22
a
to
25
a
are respectively arranged, are formed on the gate oxide film. Thereafter, to form the N
−
diffusion layers
17
and
18
respectively in the memory cell unit
2
of the DRAM and the field
3
other than the memory cell unit
2
of the DRAM, a resist pattern having a plurality of openings at prescribed positions is formed on the silicon substrate
11
. Thereafter, ions of n-type impurity are injected into the silicon substrate
11
through the openings of the resist pattern, and the N
−
diffusion layers
17
and
18
are formed in an upper portion of the silicon substrate
11
. Thereafter, the resist pattern is removed. Thereafter, to form the P
−
diffusion layer
20
in the field
3
other than the memory cell unit
2
of the DRAM, another resist pattern having an opening at a prescribed position is formed on the silicon substrate
11
. Thereafter, ions of p-type impurity are injected into the silicon substrate
11
through the opening of the resist pattern, and the P
−
diffusion layer
20
is formed in the upper portion of the silicon substrate
11
. Thereafter, the resist pattern is removed. Thereafter, a side wall spacer forming film
101
formed of silicon nitride film is deposited on the whole surface area (refer to FIG.
11
A).
Thereafter, to form the N
+
diffusion layer
19
as a source/drain diffusion layer of the NMOS in the field
3
other than the memory cell unit
2
of the DRAM, a first resist pattern
103
having an opening
102
at a prescribed position is formed on the side wall spacer forming film
101
. Thereafter, anisotropic etching is performed for a portion of the side wal

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