Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

2002-04-03

2003-01-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S579000, C438S585000

Reexamination Certificate

active

06509252

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of manufacturing field effect transistors, and particularly relates to a method of forming a gate electrode on the upper surface of a mesa layer so as to extend to the outside of the mesa layer.
2. Description of the Related Art
FIG. 1
is a sectional view showing a structure of a known field effect transistor. The known field effect transistor comprises a mesa layer
2
on a semiconductor substrate
1
, such as InP or GaAs, as shown in FIG.
1
. The mesa layer
2
has a gate electrode
3
, a source electrode
4
, and a drain electrode
5
thereon.
The gate electrode
3
of the field effect transistor shown in
FIG. 1
comprises a fine gate electrode
3
A serving as a control gate and an over gate
3
B provided on the fine gate
3
A to lower the resistance of the gate electrode
3
. The over gate
3
B has a width larger than that of the fine gate
3
A.
The mesa layer
2
has layers for operating the field effect transistor, that is, common semiconductor components required for operating the transistor, including a channel layer. Thus, the field effect transistor formed in a mesa is separated from other adjacent semiconductor devices.
FIG. 2
is a plan view of the known field effect transistor shown in
FIG. 1
, illustrating the vicinity of the end of the gate electrode
3
. The same parts are designated by similar numerals.
In the field effect transistor having the mesa layer
2
, the relationship with the relative position between the end of the gate electrode
3
and the periphery of the mesa layer
2
is important. In
FIG. 2
, the mesa layer
2
is represented as a boundary defining the periphery of the mesa layer
2
. In this field effect transistor, the end of the gate electrode
3
or at least the fine gate
3
A serving as a substantial gate electrode extends to the outside of the periphery of the mesa layer
2
, and it is across the boundary.
The reason why such an extending of the gate electrode
3
to the outside of the periphery is needed, is described as follows.
Exposures of a pattern defining the periphery of the mesa layer
2
and a gate electrode pattern, particularly a fine gate pattern, are each performed in a different step.
As a result, an alignment error is caused between the pattern defining the periphery of the mesa layer
2
and the gate electrode pattern. Even if the exposures, therefore, are performed on the condition that the periphery of the mesa layer
2
is aligned with the end of the gate electrode
3
, unfortunately the end of the gate electrode
3
occasionally lies inside the periphery. In such a case, the gate electrode
3
does not control any channel in the area of the mesa layer
2
which does not have the gate electrode
3
thereon, consequently causing a leak current between the source and the drain, flowing in a detour around the end of the gate electrode
3
.
In order to prevent the leak current, it is necessary to extend the gate electrode
3
(the fine gate
3
A) to the outside of the mesa layer
2
. The size of this protruding portion is determined in consideration of the alignment error between the pattern defining the periphery of the mesa layer
2
and the gate electrode pattern.
Nevertheless, the field effect transistor described above has often the wide dispersion of the electrical characteristics, as a result does not ensure an adequate process yield.
SUMMARY OF THE INVENTION
The inventors investigated defects in the conventional field effect transistor described above with a scanning electron microscope (SEM), and found that the end of gate electrode
3
is occasionally separated from the mesa layer
2
.
FIG. 3
is a sectional view showing the separation of the gate electrode
3
caused in the vicinity of the periphery of the mesa layer
2
. The part inscribed by a circle
301
shows this separation.
FIG. 3
shows that the fine gate
3
A and the over gate
3
B, which are included in the gate electrode
3
together, are separated from the mesa layer
2
in the vicinity of the end of the gate electrode
3
. This separated part is more likely to degrade channel controllability of the gate electrode
3
than the other non-separated part, and is therefore likely to cause leak current and the degradation of current/voltage characteristics, thus leading to a lowered process yield or a degraded performance of the field effect transistor.
Supposedly, the separation of the gate electrode
3
arises from the overhanging gate electrode
3
supported by the mesa layer
2
in a cantilever manner. The gate electrode
3
is subjected to stress in a gate electrode-forming process, such as vapor deposition, or another subsequent process. In such a gate electrode
3
as being supported in a cantilever manner, the stress is concentrated on the periphery of the mesa layer
2
where the gate electrode
3
is supported, thereby probably causing the separation. Even when the separation does not occur, the periphery of the mesa layer
2
is subjected to the stress, and therefore the gate electrode
3
cannot apply an electric field according to the design. Thus, the electrical characteristics of the field effect transistor fluctuate.
The following describes how the general field effect transistor has such an overhanging gate electrode, with reference to a process of a gate electrode.
FIGS. 4A and 4B
are sectional views showing a known process of a gate electrode. First, as shown in
FIG. 4A
, a resist for forming the fine gate
3
A is coated on the substrate
1
having the mesa layer
2
thereon to form a resist layer
10
. Although other resist layers are required to form the over gate
3
B, they are omitted from the description for the sake of clarity.
The resist layer
10
is formed so that the thickness thereof on the mesa layer
2
has a thickness sufficient to form the gate electrode
3
, for example, in this case, a thickness larger than the height of the fine gate
3
A. In the area of the resist layer
10
which the mesa layer
2
does not underlie, the surface of the resist layer
10
gradually slopes down from the periphery of the mesa layer
2
to the outside. The gradient of this slope depends on the viscosity and the curing condition of the resist for the resist layer
10
. The thickness of the resist layer
10
, therefore, does not decrease suddenly at the periphery of the mesa layer
2
.
Thus, the resist layer
10
has a larger thickness in the vicinity of the mesa layer
2
than at the part overlying the mesa layer
2
and at the part far away from the mesa layer
2
.
The amount of exposure of the gate electrode pattern, more specifically the fine gate pattern in this case, must be as small as possible. This is because an increased amount of exposure, both of light exposure and electron beam exposure, leads to an unsharped image. In particular, when an extremely fine technique is required as in the case of the gate electrode
3
, the amount of exposure is crucial.
However, since the resist layer
10
has a larger thickness in the vicinity of the mesa layer
2
, this minimum amount of exposure, which is followed by development, results in a non-exposed area
10
B left under an exposed area
10
A, as shown in FIG.
4
B.
After the exposed area
10
A is removed, the resist layer
10
is provided with a material for the gate electrode
3
thereon, and then the gate electrode
3
will be formed by a lift-off process. At this point, the residual non-exposed area
10
B is also provided with the material for the gate electrode
3
thereon, and is removed in the following lift-off process. Thus, the gate electrode
3
overhangs in a cantilever manner. As described above, the non-exposed area
10
B which is not removed before providing the electrode material causes the gate electrode
3
to overhang.
On the other hand, the thickness at the part far away from the mesa layer
2
is equal to the thickness at the area overlying the mesa layer
2
. If the gate electrode pattern is extended to the part far away from the mesa layer
2
, the non-exposed ar

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