Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1999-10-13

2002-10-08

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S725000, C438S353000, C438S700000, C438S723000, C438S724000

Reexamination Certificate

active

06461977

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to a method of etching, and more particularly to an etching method using a silicon nitride stopper for forming a self aligned direct contact to be used in a memory cell such as RAM (Random Access Memory) and SRAM (Static Random Access Memory).
Conventional methods of selectively etching a silicon nitride film include wet etching using hot phosphoric acid, and dry etching using CH
2
F
2
or CH
3
F as disclosed in Japanese Patent Publication No. 6-12765.
However, in a memory cell portion in which a self aligned direct contact is to be formed using a silicon nitride stopper, if the silicon nitride film provided as the stopper layer is removed by wet etching, which will proceed isotropically, a problem will arise that the silicon nitride film cannot be left on the sidewall portion of a pattern as desired.
Further, if a parallel-plate type reactive ion etching system (RIE) is employed with conventionally known reactive gases such as CF
4
and CHF
3
, each rate will become higher at the sidewall portion of a pattern than at the bottom of the hole due to sputtering effect, and thus it is difficult to form a sidewall of the silicon nitride film with a necessary height. Moreover, if the above-mentioned dry etching method as disclosed in Japanese Patent Publication No. 6-12765 is employed, as the etch selectivity of a silicon oxide film to a silicon nitride film is 10 or higher, etching will stop at the silicon oxide film located beneath the silicon nitride film, and thus an electrical contact fails.
SUMMARY OF THE INVENTION
The present invention is directed to solve the problems described above. An object of the invention is therefore to provide an improved etching method permitting the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern.
A first aspect of the present invention relates to an etching method of forming a sidewall spacer of a silicon nitride film at the sidewall of a stepped pattern in a self-alignment manner. The silicon nitride film formed to cover the pattern is dry-etched employing mixed gas plasma containing CH
2
F
2
and O
2
.
In this dry etching, the etch selectivity can easily be altered depending on the partial pressure of oxygen, since the mixed gas plasma including CH
2
F
2
and O
2
is employed.
According to a second aspect of the present invention, the silicon nitride film is formed to cover the pattern with an oxide film therebetween.
Consequently, the silicon nitride film can be left at the sidewall with much more thickness, while generation of hot carriers is restricted.
According to a third aspect of the present invention, the etching is conducted by setting the mixture ratio of O
2
to CH
2
F
2
between 25 and 40%.
As a result, the etch selectivity of a silicon oxide film to a silicon nitride film can be made within the range from 2 to 3.
According to a fourth aspect of the present invention, after the etching of the silicon nitride film, the oxide film is etched by setting the etch selectivity of the oxide film to the silicon nitride film to 1 or lower.
As a result, a higher sidewall of the silicon nitride film can be formed.
According to a fifth aspect of the present invention, the silicon nitride film is etched employing an etching mask having an opening with an opening diameter of 0.1 to 0.5 &mgr;m, making an etching condition such that the etch rate of the silicon nitride film becomes faster as the opening area becomes smaller.
As the etching of a silicon nitride film for forming a self aligned direct contact is performed under this condition, the etch rate at the bottom of the hole increases, while the rate becomes controllable at the silicon nitride sidewall portion having a hole diameter made large.
According to a sixth aspect of the present invention, the etching described above is performed when forming a direct contact on a memory cell structure.
The resulting memory cell is provided with a silicon nitride film having a sufficient film thickness at the sidewall portion of a pattern.
According to a seventh aspect of the present invention, the etching is conducted using a parallel-plate type etching system.
Thus the present invention can be implemented in a general-purpose etching system.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4529476 (1985-07-01), Kawamoto et al.
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5350705 (1994-09-01), Brassington
patent: 5462896 (1995-10-01), Komura et al.
patent: 5726100 (1998-03-01), Givens
patent: 5994227 (1999-11-01), Matsuo et al.
patent: 6-12765 (1994-02-01), None
patent: 7-161702 (1995-06-01), None
patent: 8-97186 (1996-04-01), None
Korean Office Action dated Sep. 7, 2000 with English translation.

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