Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-01
2002-06-25
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S723000, C438S724000, C438S701000, C438S702000, C438S703000, C438S719000, C438S695000
Reexamination Certificate
active
06410452
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device having a trench isolation structure and more particularly to a method of manufacturing a nonvolatile semiconductor memory having a trench isolation structure.
2. Description of the Related Art
To form a semiconductor device, a plurality of devices is formed on one semiconductor substrate so as to function as the semiconductor device. Formation of a plurality of devices on the same substrate requires electrical isolation of the devices from one another. LOCOS, a trench isolation structure or the like is generally used as a method of isolating devices. Of these methods, the trench isolation structure is used as the method of isolating devices for a micro-device, because the trench isolation structure does not have to form a thick thermal oxide film and is effective for microfabrication, as distinct from LOCOS. Semiconductor devices having the trench isolation structure are of various types. Semiconductor devices include a nonvolatile semiconductor memory having a floating gate, such as a DRAM, an SRAM, an EPROM or an EEPROM.
Semiconductor devices having a conventional trench isolation structure include a nonvolatile semiconductor memory comprising a memory cell and a peripheral circuit as shown in
FIG. 24
, for example. The memory cell and the peripheral circuit have the respective trench isolation structures, and edges of the trench isolation structures are angular as shown in a partially sectional view of FIG.
25
. The nonvolatile semiconductor memory is manufactured in the following manner. First, a silicon oxide film
102
of 10 nm thick is grown on a main surface of a p type (
001
) silicon substrate
101
by use of thermal oxidation. Subsequently, a silicon nitride film
103
of 200 nm thick is deposited on the silicon oxide film
102
by reduced pressure CVD method. Next, a resist
104
is formed into a desired pattern by photolithography, and then the silicon nitride film
103
is etched by using the resist
104
as a mask (see FIG.
26
).
Subsequently, the silicon oxide film
102
is etched by using the resist
104
as a mask, whereby trenches
105
each having a depth of about
400
nm are formed in the surface of the silicon substrate
101
, and then the resist
104
is removed (see FIG.
27
).
Furthermore, a silicon oxide film
106
of 600 nm thick is deposited by using CVD, whereby the trenches
105
are filled with the silicon oxide film
106
(see FIG.
28
). Then, the surface of the silicon oxide film
106
is polished by chemical mechanical polishing (CMP), and a predetermined amount of the silicon oxide film is etched by using a hydrogen fluoride (HF) aqueous solution. Subsequently, the silicon nitride film
103
is removed by using heated phosphoric acid, and then the silicon oxide film
102
is removed by using the hydrogen fluoride aqueous solution as an etchant, whereby trench isolations
107
are formed (see FIG.
29
).
Next, a resist
108
is formed into a desired pattern by photolithography. Then, by using the resist
108
as a mask, phosphorus ions of 2×10
13
cm
−2
are implanted with energy of 1.2 MeV in the silicon substrate
101
, and subsequently phosphorus ions of 2×10
12
cm
−2
2
are implanted with energy of 200 keV in the silicon substrate
101
. After that, heat treatment takes place at a temperature of 1000° C. under a nitrogenous atmosphere, whereby an n well region
109
is formed (see FIG.
30
).
Furthermore, a silicon oxide film
110
of 10 nm thick, which is to constitute a tunnel oxide film of a memory transistor, is grown by thermal oxidation. Then, phosphorus-doped polycrystalline silicon
111
of 100 nm thick and a silicon oxide film
112
of 100 nm thick are deposited on the silicon oxide film
110
by reduced pressure CVD method. After that, a resist is formed into a desired pattern by photolithography, and then the silicon oxide film
112
is etched by using the resist as a mask. After the resist is removed, the phosphorus-ions-doped polycrystalline silicon
111
is etched. Subsequently, ions of arsenic of 2×10
15
cm
−2
are implanted with energy of 40 keV by ion implantation. After that, heat treatment takes place at a temperature of 850° C. for 30 minutes under a nitrogenous atmosphere, whereby the ions of arsenic are activated and thus n type diffused layers
113
a
and
113
b
are formed (see FIG.
31
).
Subsequently, a silicon oxide film
114
of 800 nm thick is deposited by reduced pressure CVD method, and heat treatment takes place at a temperature of 850° C. for 30 minutes under a nitrogenous atmosphere (see FIG.
32
). Then, the silicon oxide film
114
is etched, whereby the surface of the phosphorus-ions-doped polycrystalline silicon
111
is exposed (see FIG.
33
).
Subsequently, a three-layer insulating film
115
comprising a silicon oxide film of 5 nm thick, a silicon nitride film of 10 nm thick and a silicon oxide film of 5 nm thick is deposited by reduced pressure CVD method (see FIG.
34
).
Next, the memory cell is coated with a resist by photolithography, and the three-layer insulating film
115
, the phosphorus-ions-doped polycrystalline silicon
111
and the silicon oxide film
110
on the substrate surface, which are to constitute the peripheral circuit, are removed. After that, the resist is removed (see FIG.
35
).
After that, a silicon oxide film
116
of 30 nm thick, which is to constitute a gate oxide film of a transistor of the peripheral circuit, is grown by use of thermal oxidation (see FIG.
36
). In this case, in the memory cell, the silicon nitride film in the three-layer insulating film
115
prevents thermal oxidation of an underlayer.
Subsequently, phosphorus-ions-doped polycrystalline silicon
117
of 200 nm thick and a silicon oxide film
118
of 200 nm thick are deposited by reduced pressure CVD method. A resist is formed into a desired pattern by photolithography, then the silicon oxide film
118
is etched by using the resist as a mask, and then the resist is removed. After that, the phosphorus-ions-doped polycrystalline silicon
117
, which is to constitute a gate electrode of the transistor of the peripheral circuit, is etched by using the silicon oxide film
118
as a mask. At the same time, the phosphorus-ions-doped polycrystalline silicon
117
, which is to constitute a control gate of the memory transistor, is etched, and then the resist is removed (see FIG.
37
).
A resist is formed on the peripheral circuit by photolithography, and then the three-layer insulating film
115
and the phosphorus-ions-doped polycrystalline silicon
111
are etched by using the silicon oxide film
118
of the memory cell as a mask, whereby a floating gate electrode
111
of the memory transistor is formed.
Next, a resist is formed into a desired pattern by photolithography, then ions of arsenic of 3×10
15
cm
−2
are implanted with energy of 50 keV by using the resist as a mask, and then the resist is removed. A resist is again formed into a desired pattern by photolithography, and then ions of BF
2
of 3×10
15
cm
−2
are implanted with energy of 30 keV by using the resist as a mask. After that, heat treatment takes place at a temperature of 800° C. for 30 minutes under a nitrogenous atmosphere, whereby an n type diffused layer
119
of an n-channel transistor of the peripheral circuit and a p type diffused layer
120
of a p-channel transistor thereof are formed (see FIG.
38
).
Furthermore, boron phosphorus glass
121
of 1 &mgr;m (1000 nm) thick is deposited by CVD. After that, heat treatment takes place at a temperature of 850° C. for
30
minutes under a nitrogenous atmosphere, whereby the boron phosphorus glass
121
is thermally shrunk. Subsequently, a resist is formed into a desired pattern by photolithography, and then the boron phosphorus glass
121
is etched by using the resist as a mask, whereby a contact hole is opened. After that, an aluminum-silicon-copper (Al—Si—Cu) alloy film
122
is deposited b
Goudreau George
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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