Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-06-29
2002-08-06
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S693000, C438S750000, C438S005000, C438S014000, C216S088000, C216S089000, C216S084000, C216S105000, C216S018000
Reexamination Certificate
active
06429134
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186990, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor device, which includes a polishing step by means of a CMP (Chemical Mechanical Polishing) method.
In the field relating to the manufacture of semiconductor device in recent years, due to a prevailing trend to further enhance the integration and performance of a semiconductor device, various fine processing techniques have been studied and developed. Among them, the aforementioned CMP method is one of the essential techniques, which is indispensable for forming a buried structure such as a buried metallic wiring or a buried element isolation.
The buried structure of this kind, for example a buried metallic wiring has been conventionally formed by making use of the CMP as follows. Namely, a stopper film is deposited on the surface of an interlayer insulating film, and then, these stopper film and interlayer insulating film are patterned to form a wiring groove. Thereafter, a metallic film is deposited over the interlayer insulating film to a thickness larger than the depth of the wiring groove. After the polishing time required for achieving the just-polishing of the metallic film is estimated from the initial film thickness of the metallic film, the metallic film is subjected to a polishing by means of the CMP method for this estimated time period (i.e. the estimated just-polishing time), thereby selectively removing the redundant portion of the metallic film which is disposed outside the wiring groove, leaving only the metallic film which is disposed inside the wiring groove, thus forming a buried metallic wiring.
However, this conventional method of forming a buried wiring is accompanied with the following problems. Namely, due to a difference in polishing rate depending on individual property of wafer or due to the changes of the polishing rate during the polishing treatment, it is impossible to minimize a difference between the polishing time required for actually achieving the just-polishing (actual polishing time) and the estimated just-polishing time, thus resulting in an over-polishing and hence, giving rise to an enlarged dishing.
Additionally, due to non-uniformity of film thickness and of polishing rate in the same film formed on a wafer, there is a possibility that even if the formation of buried wiring may have been finished processing at some locations of the same wafer as a result of the polishing, but the formation of buried wiring may not have been finished processing yet at other locations. In such a case, it may be required to set the actual polishing time longer than the polishing time t
1
of the portion of wafer where the formation of buried wiring can be finished processing at first.
Generally, the actual polishing time is set longer by a ratio of 30 to 50% than the polishing time t
1
of the portion of wafer where the formation of buried wiring can be finished at first, so that if the time t
1
is 180 seconds, the over-polishing time would become 54 to 90 seconds. Namely, the portion of wafer where the formation of buried wiring can be finished at first would be excessively polished for this over-polishing time.
Therefore, if a buried wiring having a narrow wiring interval and a buried wiring having a wide wiring interval are co-existed in a single wafer, a large erosion would be caused to generate at the region of the buried wiring having a narrow wiring interval where processing has been finished at first. Additionally, if a buried wiring having a narrow line width and a buried wiring having a wide line width are co-existed in a single wafer, a large dishing would be caused to generate at the region of the buried wiring having a wide line width where processing has been finished at first. These phenomena would become more serious as the integration of semiconductor device and the fineness of semiconductor devices are further promoted.
FIGS. 1A and 1B
illustrate the characteristics of the CMP method that has been conventionally employed in the formation of a buried wiring. If a buried wiring is to be formed, a relatively thick metal film is deposited at first, and then, the metal film is polished by means of the CMP method exhibiting a high load dependency (as shown in
FIG. 1A
, the CMP rate changes depending on the magnitude of load). In this case however, once the polishing surface becomes flat, the CMP rate would be sharply decreased. Further, when the metal film is deposited thinner, the possibility of generating the dishing would be increased.
As explained above, the conventional method of forming a buried wiring by means of the CMP method is accompanied with the problems that, since it is impossible to minimize a difference between an actual polishing time and an estimated just-polishing time, the actual polishing is inevitably resulted in an over-polishing, thereby raising the problems of erosion and enlarged dishing.
BRIEF SUMMARY OF THE INVENTION
Therefore, an object of this invention is to provide a method of manufacturing a semiconductor device, which is capable of suppressing the generation of erosion and dishing even if an over-polishing is performed on the occasion of forming a buried structure by means of CMP method.
Namely, this invention provides a method of manufacturing a semiconductor device, which comprises the steps of providing a substrate having a groove on the surface thereof, forming a burying film on the substrate to thereby fill the groove with the burying film, performing a first polishing step to polish the burying film by means of a CMP method, the polishing being suspended before the substrate is exposed, and performing a second polishing step to polish the burying film by means of a CMP method until part of the burying film which is disposed outside the groove is removed.
Further, according to this invention, there is also provided a method of manufacturing a semiconductor device, which comprises the steps of providing a substrate having a groove on the surface thereof, forming a burying film on the substrate to thereby fill the groove with the burying film, performing a first polishing step to polish the burying film by means of a CMP method, the polishing being suspended before the substrate is exposed, determining a polish-finishing time of a second polishing step on the basis of a film thickness of the burying film after the suspension of the first polishing step, and performing a second polishing step to polish the burying film by means of a CMP method until the polish-finishing time determined in the previous step runs out.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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patent: 10-128655 (1998-05-01), None
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Kubota Takeo
Nakamura Kenro
Yano Hiroyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Goudreau George
Kabushiki Kaisha Toshiba
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