Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2000-06-27
2002-04-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S007000, C438S008000, C438S015000, C438S017000, C438S018000
Reexamination Certificate
active
06365425
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor device manufacturing technique and particularly to the technique which can effectively be adapted for acquisition of positional relationship information between dust-particle/fault and pattern in the external appearance inspection.
The technique explained below has sufficiently been discussed by the inventors of the present invention on the occasion of studying and completing the present invention and the summary of this technique is as follows.
Particularly, in the pre-process of the semiconductor manufacturing process, various types of external appearance inspection apparatus are used for the external appearance inspection of a semiconductor wafer or a semiconductor chip.
These external appearance inspection apparatus outputs sizes and number of dust-particles and faults.
For example, WO98/01903 describes the inspection technique in the semiconductor manufacturing process and the uniform technique of the coordinate system in each inspection is described there.
However, it is impossible in the external appearance inspection apparatus of the technique explained above to obtain the information about the generating position of such dust-particles and faults.
Therefore, it is impossible to detect the positional relationship between dust-particle/fault and pattern and thereby here rises a problem that fatal and non-fatal dust-particles/fault cannot be determined.
Namely, on the occasion of surveying the mutual relationship between the dust-particle/fault and yield, it is required to know the fatal coefficient of dust-particle/fault detected by the external appearance inspection apparatus. For this purpose, the positional relationship information among size of dust-particle/fault, generating position of dust-particle/fault and pattern (to know that the dust-particles/fault is generated on the pattern, or at the outside of pattern or in the memory mat or peripheral circuit) is required, but it has been impossible to obtain the information about the generating position, although the external appearance inspection apparatus can output the information about size of.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device in which the fatal
on-fatal condition of the dust-particle/fault is obtained in the external appearance inspection and the result of this inspection is reflected on the semiconductor manufacturing process.
The aforementioned and other objects and features of the present invention will become apparent from the description of this specification and attached drawings.
The typical inventions among those disclosed in the present invention will be briefly explained below.
Namely, the method of manufacturing the semiconductor device of the present invention comprises a process to fetch the chip information for inspection which is the information including dust-particle/fault on the inspection chip by radiating the optical beam to the inspection chip of semiconductor wafer supported to freely move on the stage and then detecting the scattering/diffraction beam, a process to fetch the chip information for reference by radiating the optical beam to the reference chip of the semiconductor wafer which is assumed to have no dust-particle/fault, a process to obtain the dust-particle/fault information indicating position and size of dust-particle/fault on the inspection chip by comparing the inspection chip information with the reference chip information, a process to determine whether the dust-particles/fault is located on the pattern or at the outside of pattern by matching the dust-particle/fault information with the design pattern data which is the prepared pattern data, and a process to define such dust-particle/fault to the fatal condition when the dust-particle/fault is located on the pattern but to define such dust-particle/fault to the non-fatal condition when it is located at the outside of pattern.
Therefore, the fatal
on-fatal condition of dust-particles/fault can be determined.
Moreover, the method for manufacturing a semiconductor device of the present invention comprises a process to fetch first area information including dust-particle/fault of the first area of the main surface of the semiconductor wafer by radiating an optical beam to the main surface of the semiconductor wafer supported to move with the stage and then detecting the scattering/diffracting beam, a process to fetch second area information by radiating the optical beam to the second area different from the first area of the semiconductor wafer, a process to obtain the dust-particle/fault information such as position and size of the dust-particle/fault of the first area by comparing the first area information with the second area information, a process to obtain the pattern information of the second area with a Fourier image processing system by fetching the Fourier image of the second area, a process to determine existence of the pattern depending on the pattern information of the second area for the dust-particle/fault position depending on the dust-particle/fault information and a process to define the fatal dust-particle/fault when it is determined that the pattern exists in the position of dust-particles/fault and also define the non-fatal dust-particles/fault when it is determined that the pattern does not exist at the position of dust-particle/fault.
REFERENCES:
patent: 5384463 (1995-01-01), Honjo et al.
patent: 5436464 (1995-07-01), Hayano et al.
patent: 5528360 (1996-06-01), Kohno
patent: 5877035 (1999-03-01), Fujino et al.
Ikota Masami
Nakamura Hisato
Sugimoto Aritoshi
Antonelli Terry Stout & Kraus LLP
Anya Igwe U.
Hitachi , Ltd.
Smith Matthew
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