Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1999-05-13

2002-04-30

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S745000

Reexamination Certificate

active

06380089

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, especially, a method of manufacturing a semiconductor device formed on an SOI substrate.
2. Description of the Background Art
Semiconductor devices (SOI device) formed on an SOI (Silicon On Insulator) substrate have advantages such as reduced junction capacitance and improved element isolation breakdown voltage, over semiconductor devices (bulk device) formed on a bulk substrate.
FIG. 5
is a cross-sectional view of an SOI substrate
10
. The SOI substrate
10
has a structure with a buried oxide film
2
and a single crystalline silicon layer (hereinafter referred to as “SOI layer”)
3
stacked on the main surface of a silicon substrate
1
. In
FIG. 5
, the buried oxide film
2
is approximately 370 nm thick, and the SOI layer
3
is approximately 200 nm thick.
At the time of forming the substrate, the thickness of the SOI layer
3
of the SOI substrate
10
is approximately 200 nm as shown in FIG.
5
. However, in the manufacture of semiconductor devices, the SOI layer
3
has to be reduced in thickness according to specs of desired semiconductor devices, which is called a thinning process of the SOI layer
3
.
As shown in
FIG. 6
, the SOI layer
3
is thinned to a moderate thickness in a semiconductor element forming region (active region) AR of the main surface of the SOI substrate
10
.
When the thickness of the SOI layer required for the manufacture of semiconductor devices is 100 nm, for example, the SOI layer
3
of the SOI substrate
10
has to be reduced by about 100 nm since its original thickness is approximately 200 mn.
Conventionally, techniques for thermally oxidizing the SOI layer
3
have been adopted to make the SOI layer
3
thinner. More specifically, the SOI substrate
10
is heated to about 1000° C. and exposed to an oxygen atmosphere for thermal oxidation so that a 220-nm thick thermal oxide film
4
is formed on the SOI layer
3
as shown in FIG.
7
. This consumes about 100 nm of silicon which forms the SOI layer
3
, thereby reducing the SOI layer
3
to approximately 100 nm.
After the removal of the thermal oxide film
4
with a hydrofluoric acid solution, the SOI layer
3
of the SOI substrate
10
has a thickness of about 100 nm as shown in FIG.
8
.
The problem here is surplus silicon (injected silicon interstitial during oxidation), i.e., a phenomena that interstitial silicon atoms occurring in the interface between silicon and a silicon oxide film during thermal oxidation of the SOI layer
3
form crystal defects DF in the SOI layer
3
as shown in FIG.
8
. When semiconductor devices are formed in the SOI layer
3
with the crystal defects DF, abnormal leakage current will occur during operation of the devices.
FIG. 9
schematically shows an example that CMOSs (Complementary MOSs) are formed in the thinned SOI layer
3
. In
FIG. 9
, the SOI layer
3
is electrically divided into an NMOS region with a plurality of N-type MOSFETs (N-MOSFETs)
15
and a PMOS region with a plurality of P-type MOSFETs (P-MOSFETs)
25
by an element isolation film
5
formed of an insulating film such as a silicon oxide film.
The N-MOSFET
15
has a P type impurity region
14
with P-type impurities doped into the SOI layer
3
; a gate oxide film
11
formed on the P-type impurity region
14
; a gate electrode
12
formed on the gate oxide film
11
; and source/drain regions
13
with N-type impurities relatively highly doped therein which are formed in the SOI layer
3
to sandwich the P-type impurity region
14
from both sides.
The P-MOSFET
25
has an N-type impurity region
24
with N-type impurities doped into the SOI layer
3
; a gate oxide film
21
formed on the N-type impurity region
24
; a gate electrode
22
formed on the gate oxide film
21
; and source and drain regions with P-type impurities relatively highly doped therein which are formed in the SOI layer
3
to sandwich the N-type impurity region
24
from both sides.
As shown in
FIG. 9
, MOSFETs including the crystal defects DF are formed in proportion to a crystal defect density in the formation of a plurality of MOSFETs in the SOI layer
3
having the crystal defects DF. This results in characteristic anomalies and malfunction.
FIGS. 8 and 9
only schematically show the crystal defects DF in the SOI layer
3
, and actual crystal defects are more complicated. Further, it is difficult to detect the as-is status of crystal defects after the thermal oxidation for thinning the SOI layer, so that the presence of crystal defects is confirmed by manifesting the crystal defects by means of selective etching such as Secco etching.
The Secco etching refers to an etching using an etchant, so called “Secco” or an etching using as an etchant an aqueous solution of a mixture of 0.15-mol potassium dichromate (K
2
Cr
2
O
7
) and 48% of hydrofluoric acid (HF) in the ratio of 1:2. This is to manifest crystal defects by using a characteristic that the etching rate in a portion with crystal defects is higher than that in a portion with no crystal defect.
In this fashion, the conventional thinning method of the SOI layer included the thermal oxidation process of the SOI layer, so that it had a problem of causing crystal defects in the SOI layer due to the thermal oxidation.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of: preparing an SOI substrate; isotropically etching an SOI layer of the SOI substrate to a predetermined thickness with an NH
3
—H
2
O
2
—H
2
O solution; and forming semiconductor devices on the thinned SOI layer.
According to a second aspect of the present invention, in the manufacturing method of the first aspect, the ratio of components NH
3
and H
2
O
2
in the NH
3
—H
2
O
2
—H
2
O solution stands at 1:1.
According to a third aspect of the present invention, in the manufacturing method of the second aspect, the ratio of components in the NH
3
—H
2
O
2
—H
2
O stands at 1:1:5 and a temperature of the solution ranges from 50° C. to less than 100° C.
According to a fourth aspect of the present invention, in the manufacturing method of the second aspect, the ratio of components in the NH
3
—H
2
O
2
—H
2
O stands at 1:1:1 and a temperature of the solution ranges from 50° C. to less than 100° C.
A fifth aspect of the present invention is directed to a method of manufacturing a semiconductor device comprising the steps of: preparing an SOI substrate; isotropically etching an SOI layer of the SOI substrate to a predetermined thickness by means of down flow etching, wherein plasma is produced by excitation of a predetermined etching gas by high frequency or microwaves and radicals which are chemically active atoms or molecules included in the plasma are transported to the SOI substrate along a flow of the etching gas to be used as etching species; and forming semiconductor devices on the thinned SOI layer.
According to a sixth aspect of the present invention, in the manufacturing method of the fifth aspect, the etching gas is either of mixed gas of CF
4
and O
2
, mixed gas of NF
3
and O
2
, Cl
2
gas, mixed gas of Cl
2
and NF
3
, or NF
3
gas.
In the method of manufacturing a semiconductor device of the first aspect, silicon atoms are removed progressively from the surface of the SOI layer since the SOI layer is isotropically etched to a predetermined thickness with the NH
3
—H
2
O
2
—H
2
O solution. Thus, surplus silicon is not produced in the SOI layer, which prevents occurrence of crystal defects in the SOI layer due to surplus silicon. This results in prevention of occurrence of characteristic anomalies or malfunction due to crystal defects when semiconductor devices are formed in the thinned SOI layer.
In the method of manufacturing a semiconductor device of the second aspect, the ratio of components NH
3
and H
2
O
2
in the NH
3
—H
2
O
2
—H
2
O solution stands at 1:1. This prevents surface roughness of the SOI layer.
In the method of manufacturing a semico

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