Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-12-08
2002-04-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S529000, C438S975000
Reexamination Certificate
active
06368937
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device to form a positioning mark in the element isolating process.
2. Description of the Related Art
In recent years, the manufacture of semiconductor devices is often accompanied by many lithographic processes. In this case, the positioning mark is formed as the reference to accurately align the mask position.
This positioning mark can be formed by forming a “step” on a base film or a substrate by selective etching or by selective oxidation. A position may be detected by optically detecting such a step for the positioning between the semiconductor substrate and the mask.
For example, there is provided a technique called LOCOS (Local Oxidation of Silicon) as a method of element isolation in a semiconductor device. In this technique, the predetermined area on the surface of silicon substrate is selectively oxidized thermally using a silicon nitride film as an oxidation preventing mask and the oxide film formed thereby is defined as an element isolation area. An oxide film formed in the element isolating film is generally referred to as a “field oxide film”.
Since this field oxide film is formed by utilizing the step for the silicon substrate, the mask of the next process can be easily aligned for the preceding process by utilizing this step as the positioning mark.
However, the element isolation by the LOCOS method has the following disadvantages.
One problem is the “bird's beak” phenomenon. This “bird's beak” widens the field oxide film area, resulting in a problem that the element isolation area becomes narrower.
Another problem is the “thinning effect” phenomenon. In this case, when the width of element isolating area becomes narrow, the film becomes thinner. Therefore, there arises a problem in that element isolation is no longer perfect.
These problems are well-known, but when element size is relatively large, the influences of the bird's beak and the thinning phenomena have not been significant.
However, with further improvement in micro-miniaturization of a semiconductor device, not only the element but also an element isolation area are also micro- miniaturized and thereby these problems have become significant.
As an element isolation structure which does not generate such a problem, trench isolation has been known in which a trench is formed on a silicon substrate and an insulator or a polycrystalline silicon is buried therein. Of the trench isolation method, a structure referred to as an STI (Shallow Trench Isolation) in which an element isolation is performed with the comparatively shallow trench having a depth of about 1 &mgr;m or less is attracting attention and this STI structure is now being investigated for practical use.
However, even in this s forming process, there is a problem in that if it is attempted to apply the STI structure to the positioning mark, a sufficient step cannot be attained and therefore it cannot be utilized as the positioning mark. Therefore, it is difficult to directly use the positioning mark attained by using the field oxide film even in the STI structure.
Therefore, even in the case where an STI is used, the mark forming process explained below may be thought as a method to maintain in the element forming area the flatness of the burying element isolation structure and to realize the mark structure which may be stably detected.
Namely, the element isolating method utilizing an STI will be explained with reference to
FIGS. 6-8
. In the Figs., x indicates an element forming area, while y indicates a positioning mark forming area.
First, as illustrated in
FIG. 6A
, after an oxide film
102
is formed in the thickness of 10 nm on the silicon substrate
101
, a silicon nitride film
103
is formed in with a thickness of 100 nm on the entire surface by the CVD method. Subsequently, an aperture is formed by etching the silicon nitride film
103
and the oxide film
102
with the patterned resist mask (not illustrated) and trenches
104
a
,
104
b
are formed, each having a depth of about 0.5 &mgr;m by the RIE (Reactive Ion Etching) method on the lower silicon substrate
101
.
Next, as illustrated in
FIG. 6B
, after the resist mask is peeled, the internal wall of the trench is thermally oxidized to form a thermally oxidized film (not illustrated) having a thickness of 5 nm. The silicon oxide film
105
is formed to have a thickness of 1 &mgr;m on the entire surface by the CVD method and the inside of the trenches
104
a
,
104
b
are filled with silicon oxide film
105
.
Next, as illustrated in
FIG. 6C
, after adequate heat treatment is applied, the silicon oxide film
105
on the silicon nitride film
103
is removed by CMP (Chemical Mechanical Polishing) or by RIE and a burying oxide film
105
a
in the element forming area x and a burying oxide film
105
b
in the positioning mark forming area y are formed.
Next, as illustrated in
FIG. 7D
, the silicon nitride
103
is removed using phosphoric acid. Next, the oxide film
102
on the silicon substrate
101
is removed by hydrofluoric acid. In this case, the step between the burying oxide films
105
a
,
105
b
and the silicon substrate
101
becomes almost flat in the level difference under about 30 nm. Moreover, the surface of silicon substrate
101
is thermally oxidized to form a thermally oxidized film
106
on the entire surface.
Next, as illustrated in
FIG. 7E
, the p-type and n-type impurity ions are selectively implanted several times to the silicon substrate
101
in different energies and different dosages and the wells
107
a
to
107
f
are formed by application of heat treatment for activation of such impurity.
Next, as illustrated in
FIG. 7F
, in view of protecting the element forming area x, the resist
108
is coated, the resist
108
is selectively removed in the positioning mark forming area y using the lithography method to expose only the substrate surface at the area near the mark through the aperture
108
a.
In this case, a distance of about 200 &mgr;m is maintained between the element forming area x and positioning mark. Therefore, since higher accuracy is not required for the positioning in the lithography, the patterning of the resist
108
can be realized easily even if the accurate mark position is not detected.
Next, a step
108
b
as deep as about 400 nm is formed by selectively removing the thermally oxide film
106
and burying oxide film
105
b
in the area y using NH
4
F etching. In this case, since the element forming area x is protected by the resist
108
, the burying oxide film
105
a
is never etched and flatness of the element forming area x can be maintained.
Next, as illustrated in
FIG. 8G
, the resist
108
is removed. Thereby, the burying element isolation having the positioning mark consisting of the step
108
b
as deep as about 400 nm can be realized while keeping the flatness of the element forming area x. Thereafter, the thermal oxide film
106
is removed using hydrofluoric acid.
Next, as illustrated in
FIG. 8H
, a gate oxide film
109
is formed by the thermal oxidation of the surface of the element forming area of the silicon substrate
101
. A polysilicon layer
110
which will become the gate electrode is formed on the gate oxide film
109
. The photoresist is formed to the entire surface and the positioning is performed by utilizing the step of the polysilicon layer
110
formed on the positioning mark in order to form the resist pattern
111
.
Next, as illustrated in
FIG. 8I
, using the resist pattern
111
, the polysilicon layer
110
is etched to form a gate electrode
110
a
. Moreover, impurity diffused layers (not illustrated) which will become the source and drain are formed on the silicon substrate
101
in both sides of the gate electrode
110
a.
In general, in the manufacture of a semiconductor device, reduction of manufacturing costs is desirable and an increase in the number of manufacturing proce
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Niebling John F.
Pompey Ron
LandOfFree
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