Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-07-05
2001-11-06
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S255000, C438S396000
Reexamination Certificate
active
06313005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices having a capacitor above a semiconductor substrate, such as of a hollow cylindrical capacitor structure.
2. Description of the Background Art
In manufacturing a semiconductor device having a capacitor above a semiconductor substrate, such as DRAMs having a memory cell of a hollow cylindrical capacitor structure, it has been necessary to form a storage node direct contact for electrical connection between a storage node electrode disposed above the capacitor and the semiconductor device components disposed on the semiconductor substrate.
FIGS. 9
to
11
are cross sections illustrating steps in a conventional method of manufacturing a DRAM having a memory cell of a hollow cylindrical capacitor structure. Specifically,
FIGS. 9 and 10
show intermediate stages of manufacture, and
FIG. 11
shows the final product.
Referring to
FIG. 9
, an interlayer BP (Boron, Phosphorus)-TEOS layer
22
, interlayer BP-TEOS layer
23
, SS (Storage node Stopper) nitride film
24
and interlayer BP-TEOS layer
25
are disposed on a semiconductor substrate
21
. Bit line
29
is selectively disposed on the interlayer BP-TEOS layer
22
. The structure so constructed is subjected to photolithography and etching process, to form a hole extending through the interlayer BP-TEOS layer
25
, SS nitride layer
24
, interlayer BP-TEOS layer
23
and interlayer BP-TEOS layer
22
, thereby to provide a plug
30
composed of polysilicon in the hole.
Referring to
FIG. 10
, an interlayer BP-TEOS layer
26
is formed on the interlayer BP-TEOS layer
25
including the plug
30
, an upper TEOS layer
27
is formed on the interlayer BP-TEOS layer
26
, and a patterned resist
31
is formed on the upper TEOS layer
27
.
By using the resist
31
as a mask, an etching process of the upper TEOS layer
27
and interlayer BP-TEOS layer
26
is performed to form a hollow cylindrical groove for metallization (not shown). Then, as shown in
FIG. 11
, a storage node electrode
34
, capacitor insulating film
36
and cell plate node electrode
37
are formed successively, thereby obtaining a capacitor
38
of a hollow cylindrical structure consisting of these components
34
,
36
and
37
. At this time, the plug
30
functions as a storage node direct contact (i.e., a direct contact between the storage node electrode
34
of the capacitor
38
and a component disposed on the surface of the semiconductor substrate
21
).
The conventional method of manufacturing DRAMs of a hollow cylindrical capacitor structure is performed as described above, which necessitates the step of forming the plug
30
for storage node direct contact. This step therefore causes an increase in the number of steps and in the cost of manufacture.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method of manufacturing a semiconductor device comprises the steps of: (a) forming successively first and second layers on a semiconductor substrate; (b) forming a hole so as to extend through the first and second layers; (c) forming a groove for metallization in the second layer so as to selectively extend through the second layer including the hole; (d) forming a first electrode layer on the bottom and side of the groove for metallization, while filling the inside of the hole remained, the first electrode layer having a contact part filled in the inside of the hole remained and an electrode part disposed on the bottom and side of the groove for metallization; and (e) forming successively an insulating film and a second electrode layer on the electrode part of the first electrode layer, thereby to obtain a capacitor consisting of the electrode part, the second electrode layer and the insulating film.
With this method, in the step (d) it is possible to form the first electrode layer which includes the contact part filled in the hole remained and the electrode part disposed on the bottom and side of the groove for metallization.
Therefore, the contact part and electrode part, which have conventionally been formed in different steps, can be formed at the same time, thereby permitting reductions in the number of steps and in the cost of manufacture.
According to a second aspect, the method of the first aspect further comprises the steps of: (f) filling the hole to form an auxiliary layer, which step is performed after the step (b) and before the step (c); and (g) removing the auxiliary layer in the hole remained, which step is performed after the step (c) and before the step (d).
With this method, the hole is filled to form an auxiliary layer in the step (f), which is performed after the step (b) and before the step (c), and the auxiliary layer protects the semiconductor substrate from damage to be exerted via the hole, in the step (c).
According to a third aspect, the method of the second aspect is characterized in that: the step (a) includes the steps of (a-1) forming the first layer on the semiconductor substrate, (a-2) forming a stopper layer on the first layer, and (a-3) forming the second layer on the stopper layer; that the step (b) includes the step of forming the hole so as to extend through the first layer, the stopper layer and the second layer; that the step (c) includes the steps of (c-1) forming a resist patterned on the second layer, and (c-2) performing an etching process of the second layer by using the resist as a mask, to form the groove for metallization, the stopper layer having etching resistance to the etching process; and that the step (g) includes the step of removing the resist in addition to the auxiliary layer.
With this method, when in the step (c-2) the groove for metallization is formed by performing an etching process of the second layer by using the resist as a mask, it is able to reliably prevent removal of the first layer below the stopper layer, because the stopper layer has etching resistance to the etching process.
Preferably, in the method of the third aspect, the first and second layers include a TEOS layer, and the stopper layer includes a nitride film.
According to a fourth aspect, the method of the third aspect is characterized in that: the step (f) includes the step of forming the auxiliary layer on the second layer and also in the inside of the hole; that the step (c-1) includes the steps of (c-1-1) forming a resist material on the entire surface of the second layer, and (c-1-2) patterning the resist material to form the resist; and that the auxiliary layer includes an anti-reflective coating to prevent the reflection of light at the time of exposure for patterning in the step (c-1-2).
In this method, since the auxiliary layer includes the anti-reflective coating to prevent the reflection of light at the time of exposure for patterning in the step (c-1-2), the exposure process for the patterning can be performed with high precision.
Preferably, in the method of the fourth aspect, the anti-reflective coating includes a bottom anti-reflective coating.
According to a fifth aspect, the method of the third aspect is characterized in that: the auxiliary layer and the resist have a characteristic of being able to be removed by an identical removing means; and that the step (g) includes the step of removing the auxiliary layer and the resist at the same time, by using the identical removing means.
With this method, the number of steps can be reduced because of the step (g) in which the auxiliary layer and resist are removed at the same time, by a predetermined removing means.
Preferably, in the method of the fifth aspect, the identical removing means includes ashing cleaning.
According to a sixth aspect, the method of the third aspect further comprises the step of (h) forming a first component of a DRAM in the surface of the semiconductor substrate, which step is performed before the step (a), and is characterized in that: the capacitor includes a memory cell capacitor for the DRAM, and the contact part of the first electrode layer is electrically connected to the first c
Kido Shigenori
Kinugasa Akinori
Kishida Takeshi
Mametani Tomoharu
Matsufusa Jiro
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wilson Christian D.
Zarabian Amir
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