Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-06-18
2001-03-27
Fahmy, Wael (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S255000, C438S396000
Reexamination Certificate
active
06207527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device having a capacitor largely extending in the direction orthogonal to the semiconductor substrate.
2. Description of the Background Art
Conventional capacitors have their area reduced in the direction parallel to the main surface of the semiconductor substrate and increased in the direction orthogonal to the main surface of the semiconductor substrate in order to secure sufficient capacitor capacity in a limited two-dimensional region. Therefore, in a capacitor for a 64 mbit DRAM (Dynamic Random Access Memory) and on, the simple large thickness type structure, fin-type structure, cylindrical structure or the like is employed. In order to enlarge the opposing area between the electrodes of a capacitor in the same structure, a storage electrode, the lower electrode of a capacitor is chemically or thermally treated in order to increase the surface area of the lower electrode of the capacitor. According to a known method of increasing the surface area of the lower electrode of a capacitor, for example, silicon crystals as described in Appl. Phys. Vol. 61, No. 11, p.1147 (1992) are allowed to grow on the surface of the storage electrode and irregularities are formed on the surface.
A conventional method of manufacturing a semiconductor device having a capacitor will be described in conjunction with
FIGS. 17
to
26
. In this method, a gate electrode
103
is formed on a semiconductor substrate
101
with a gate oxide film
102
therebetween. Then, source/drain regions
104
are formed on both sides of gate electrode
103
as shown in FIG.
17
. An interlayer oxide film
105
is formed to cover gate oxide film
102
and gate electrode
103
. Then, using a resist film
106
patterned on interlayer oxide film
105
as a mask, a contact hole
105
a
connecting source/drain region
104
is formed through interlayer oxide film
105
as shown in FIG.
18
. Subsequently, after removal of the resist film, as shown in
FIG. 19
, contact hole
105
a
is filled with a contact plug
107
including polycrystalline silicon containing an impurity. Then, an upper interlayer oxide film
108
is formed on interlayer oxide film
105
.
Then, as shown in
FIG. 20
, using a resist film
109
patterned on upper interlayer oxide film
108
as a mask, a hole
108
a
is formed on upper interlayer oxide film
108
by dry etching to expose an upper surface of contact plug
107
. As shown in
FIG. 21
, a polycrystalline silicon film
110
including an impurity to be a storage electrode is formed to have a prescribed thickness along the side surface
108
a
and bottom surface
108
c
of first hole
108
a
and the upper surface
108
b
of interlayer oxide film
108
. Irregularities are formed on the surface of polycrystalline silicon film
110
containing an impurity and as shown in
FIG. 22
, a polycrystalline silicon film
111
having irregularities is formed. A resist film
112
is formed to fill the side and bottom surfaces
111
a
and
111
c
of a second hole formed by polycrystalline silicon film
111
having the irregularities, and the state as shown in
FIG. 23
is attained.
Only polycrystalline silicon film
111
with irregularities formed on the upper surface
108
b
of interlayer oxide film
108
is removed by dry etching, and as shown in
FIG. 24
, a storage electrode
115
is formed. As shown in
FIG. 25
, resist film
112
is removed and a capacitor dielectric film
116
is formed to cover the surface of storage electrode
115
and the upper surface
108
b
of interlayer oxide film
108
. A cell plate electrode
117
is formed to cover the side surface
116
a
and the bottom surface of a third hole formed by capacitor dielectric film
116
and the upper surface
116
b
of the capacitor dielectric film, and the semiconductor device having a DRAM with a capacitor electrode as shown in
FIG. 26
is completed.
However, in the step of etching back polycrystalline silicon film
111
with irregularities formed on the upper surface
108
b
of interlayer oxide film
108
in the state shown in
FIG. 23
, if a device which ends the etching process at the time the upper surface
108
b
of interlayer oxide film
108
is exposed is used, as shown in
FIG. 24
, the irregularities on the upper surface
111
b
of polycrystalline silicon film
111
causes etching residue
150
having a corresponding irregular shape to remain. Therefore, as shown in
FIG. 26
, capacitor dielectric film
116
and cell plate electrode
117
are sequentially formed on etching residue
150
. Etching residue
150
adversely affects the state of a stack of layers formed on interlayer insulating film
8
in succeeding steps. Etching residue
150
having conductivity could short-circuit another conductive layer and storage electrode
115
.
SUMMARY OF THE INVENTION
The present invention is directed to a solution to the above-described problems, and it is an object of the present invention is to provide a method of manufacturing a semiconductor device including a capacitor, according to which the conductive etching residue is restrained from adversely affecting the state a stack of layers to be formed on the interlayer insulating film in succeeding steps and short-circuiting another conductive layer and a storage electrode, so that the yield can be improved.
The method of manufacturing a semiconductor device includes the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a first hole through the interlayer insulating film; forming a first layer including a semiconductor layer having a prescribed thickness so that a second hole is formed on side and bottom surfaces of the first hole and an upper surface of the interlayer insulating film; forming irregularities on a surface of the first layer; implanting ions into the upper surface of the first layer formed at least on the upper surface of the interlayer insulating film; removing only the first layer formed on the upper surface of the interlayer insulating film, thereby forming a first conductive layer; forming a dielectric film having a prescribed thickness to cover at least the surface of the first conductive layer and have a third hole on side and bottom surfaces of the second hole; and forming a second conductive layer to cover at least a surface of the dielectric film.
By this manufacturing method including the step of implanting ions into the surface of the first layer, the implanted ions can eliminate the raised portion of the irregularities formed on the surface of the first layer and fill the recessed portion. As a result, the irregularities formed on the surface of the first layer can be formed approximately parallel to the upper surface of the interlayer insulating film, and therefore, the surface of the first layer can be etched back approximately parallel to the upper surface of the interlayer insulating film. The irregularities formed on the surface of the first layer can be etched back without being left as etching residue on the upper surface of the interlayer insulating film. Therefore, the adverse effect on layers to be formed in succeeding steps and short-circuit between another conductive layer and the storage electrode caused by the etching residue of the first layer becoming conductive because of ion implantation can be restrained. Thus, if the first layer has irregularities on the surface for securing a larger area for the storage electrode of the capacitor, the yield of semiconductor devices having such a capacitor can be improved.
If the first layer is a semiconductor layer not provided with an impurity, an impurity must be implanted to allow the layer to serve as a storage electrode, and therefore, the step of implanting ions to eliminate the irregularities on the first layer on the interlayer insulating film as well as the step of implanting ions to allow the storage electrode to have conductivity are performed so that
Inaba Yutaka
Mori Kiyoshi
Ogata Tamotsu
Tsuchimoto Junichi
Fahmy Wael
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Thomas Toniae M.
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