Method of manufacturing semiconductor device

Details Method of manufacturing semiconductor device Method of manufacturing semiconductor device

1994-06-24

1996-03-19

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 57, 437 35, 148DIG82, H01L 21265, H01L 218238

Patent

active

055003796

ABSTRACT:
In a CMOS semiconductor device, low-dose ion implant of p-type impurity and n-type impurity is successively conducted to both n-MOSFET and p-MOSFET after formation of gate electrodes. Thereafter, when source/drain regions are formed at each MOSFET, p.sup.- regions function as local punch through stoppers in the n-MOSFET and n.sup.- regions function as the local punch through stoppers in the p-MOSFET. At this time, respective doses of n-type and p-type impurities are adjusted so that lowerings of threshold values of the channel regions are almost equal to each other. Thus, short channel effect is prevented, while reducing the step of forming two resist masks. With side walls, the CMOS semiconductor device with less short channel effect and high durability to hot carrier is manufactured without increase in the step of forming the resist masks.

REFERENCES:
patent: 4649629 (1987-03-01), Miller et al.
patent: 4908327 (1990-03-01), Chapman
patent: 5170232 (1992-12-01), Narita
patent: 5171700 (1992-12-01), Zamanian
patent: 5278441 (1994-01-01), Kang et al.
patent: 5283200 (1994-02-01), Okamoto
patent: 5320974 (1994-06-01), Hori et al.
patent: 5328862 (1994-07-01), Goo

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