Method of manufacturing photodiodes

Details Method of manufacturing photodiodes Method of manufacturing photodiodes

2001-05-11

2003-04-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S700000

Reexamination Certificate

active

06551904

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing semiconductor devices, and particularly to a method of manufacturing PIN photodiodes or other photodiodes.
BACKGROUND OF THE INVENTION
Among semiconductor devices, photodiodes are diodes that generate a current upon receiving light, being used widely as light receiving devices for optical pickup devices built into CD, DVD or other optical disk drives.
Photodiodes have a structure consisting of a semiconductor with a pn junction, and by applying a reverse bias to the pn junction, the depletion layer is widened to induce a high electric field. Light absorbed mainly by the depletion layer generates electron-hole pairs, and drawn by the electric field, the electrons move toward the n-type semiconductor region and the holes move toward the p-type semiconductor region, being detected as current.
The types of said photodiodes include PIN photodiodes wherein an I layer (a p
−
layer or n
−
layer) containing a low density of conductive impurities is provided between the p layer and n layer, thus making the depletion layer more easily widened at low voltage, and avalanche photodiodes wherein a region for generating an avalanche breakdowvn is provided.
FIG.
13
(
a
) is a cross-sectional diagram of said PlN photodiode.
For example, an n
−
semiconductor layer
11
is formed upon a silicon semiconductor substrate
10
, and in the region to become the PIN diode (for example, a 100 &mgr;m×100 &mgr;m region), a p
−
semiconductor layer
12
is formed upon the surface layer region of the n
31
semiconductor layer
11
, thereby forming a pn junction.
Upon the top layer of the p
+
semiconductor layer
12
is laminated an insulating film I consisting of a first insulating film
20
, second insulating film
21
, third insulating film
22
, fourth insulating film
23
and fifth insulating film
24
. The first through fifth insulating films (
20
-
24
) may each consist of silicon oxide films formed by means of the chemical vapor deposition (CVD) method using tetraethylorthosilicate (TEOS) as the raw material, BPSG (boro-phosphosilicate glass; silicon oxide containing phosphorus and boron) films, silicon nitride films or the like.
The aforementioned insulating film I attenuates the light incident on the p
+
semiconductor layer
12
, so a hole that exposes the p
+
semiconductor layer
12
is formed in the insulating film I.
When a reverse bias is applied to the aforementioned PIN photodiode, as shown in FIG.
13
(
b
), the depletion layer V is enlarged from the pn junction surface toward the n
−
semiconductor layer
11
and p
−
semiconductor layer
12
sides.
Here, the depletion layer is enlarged so that the total number of carriers on the n side and p side become equal, so the n
−
semiconductor layer
11
side which has a lower carrier density is enlarged to a greater degree.
When light L is incident upon the aforementioned depletion layer, the light L is absorbed by the depletion layer, generating a electron-hole pair (indicated by the o symbol in FIG.
13
(
b
)) which is detected as current. When light L is absorbed by portions not in the depletion layer, an electron-hole pair is not generated (indicated by the × symbol in FIG.
13
(
b
)).
Here follows a description of the method of manufacturing the aforementioned PIN photodiode.
First, as shown in FIG.
14
(
a
), a silicon semiconductor substrate
10
is subjected to ion implantation with phosphorus or other n-type impurities to form an n
−
semiconductor layer
11
.
Next, in the PIN diode formation region (for example, a 100 &mgr;m×100 &mgr;m region), ion implantation with boron or other p-type impurities is performed using a resist mask (not shown) to form a p
+
semiconductor layer
12
upon the surface layer region of the n
−
semiconductor layer
11
. Note that the n
−
semiconductor layer
11
may also be formed by epitaxial growth.
Next, as shown in FIG.
14
(
b
), upon the entire surface of the top layer of the p
+
semiconductor layer
12
is laminated an insulating film I consisting of a first insulating film
20
, second insulating film
21
, third insulating film
22
, fourth insulating film
23
and fifth insulating film
24
.
Here, the first through fifth insulating films (
20
-
24
) may be formed by depositing silicon oxide films formed by means of the CVD method using TEOS as the raw material, depositing BPSG films, or they may be laminated by a step of depositing silicon nitride films by the CVD method or the like.
Aluminum or other wiring is normally formed in regions not shown in the figure between the aforementioned first through fifth insulating films (
20
-
24
), and in this case, the first through fifth insulating films (
20
-
24
) are formed such that they reduce the differences in level arising due to the aforementioned wiring and the like.
In the state shown in FIG.
14
(
b
), the insulating film I is formed upon the top layer of the depletion layer region which extends from the interface between the p
+
semiconductor layer
12
and n
−
semiconductor layer
11
which is the light-sensitive region, and this insulating film I attenuates the light incident on the p
+
semiconductor layer
12
, so a hole that exposes the p
+
semiconductor layer
12
is normally formed in the insulating film
1
.
The aforementioned hole is formed by RIE (reactive ion etching) or another type of dry etching or wet etching after the formation of a resist film with the aforementioned hole pattern.
However, in the aforementioned conventional process of manufacturing PIN photodiodes, at the time of forming the hole that exposes the p
+
semiconductor layer in the insulating film, peeling of the laminated insulating films may occur, or leakage may occur at the pn junction of the diode, and other problems may also occur.
FIG. 15
is a cross-sectional diagram showing the state at the time of formation of the hole H in the aforementioned insulating film I that exposes the p
+
semiconductor layer
12
, after the resist film R with the hole pattern is formed, and after the dry etching is performed.
In the aforementioned method, since overetching still occurs after the first insulating film corresponding to the bottom of the hole is removed by etching, the surface of the p
+
semiconductor layer
12
is hit directly by etching gas and suffers damage D, becoming the cause of occurrence of leakage.
FIG. 16
is a cross-sectional diagram showing the state at the time of formation of the hole H in the aforementioned insulating film I that exposes the p
+
semiconductor layer
12
, after the resist film R with the hole pattern is formed, and after the wet etching is performed.
In the aforementioned method, in contrast to dry etching, the surface of the p
+
semiconductor layer
12
is not hit directly by etching gas and does not suffer damage, but the etching rates of the first through fifth insulating films (
20
-
24
) which make up the insulating film I are different depending on the composition or film quality or the like, so films with high etching rates X are gouged out from the inside wall surface of the hole, and peeling of the film due thereto may occur.
The present invention came about in light of the aforementioned problem and thus the object of the present invention is to provide a method of manufacturing PIN diodes or other diodes, said method being a method of manufacturing semiconductor devices whereby an insulating film as the upper layer of the diode can be removed without causing film peeling or leakage.
SUMMARY OF THE INVENTION
In order to achieve the aforementioned object, the method of manufacturing photodiodes according to the present invention comprises: a step of forming a second semiconductor layer of a second conduction type upon the primary surface of a first semiconductor layer of a first conduction type, a step of forming a mask layer upon said second semiconductor layer, a first etching step

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