Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal
Patent
1975-03-21
1976-10-12
Rutledge, L. Dewayne
Metal treatment
Process of modifying or maintaining internal physical...
Chemical-heat removing or burning of metal
29571, 29577, 29578, 357 23, 357 41, 357 45, H01L 2122, H01L 2710
Patent
active
039855910
ABSTRACT:
A method of making a metal oxide semiconductor large scale integration circuit incorporating both parallel and series gate matrix circuits using a self-alignment technique is provided, wherein a plurality of diffused regions of a conductivity type opposite to that of a silicon substrate are formed in the silicon substrate to extend substantially parallel to one another, a silicon dioxide layer as a field oxide layer is formed over the entire surface area of this structure, a hole is cut into the dioxide layer at each of selected portions thereof lying between the diffused regions, a gate oxide layer is formed in each of the holes, and then a plurality of gate electrode layers are strip shaped and located transverse to the diffused regions with each of the gate oxide layers having at least a portion of the associated gate electrode layer placed thereon, thereby providing a plurality of MOS field-effect transistors. This method makes it possible to produce parallel gate matrix circuits by the use of a diffusing mask for self-alignment as a mask pattern for forming the gate oxide layer.
REFERENCES:
patent: 3519504 (1970-07-01), Cuomo
patent: 3541543 (1970-11-01), Crawford et al.
patent: 3608189 (1971-09-01), Gray
patent: 3702985 (1972-11-01), Proebsting
patent: 3739238 (1973-06-01), Hara
patent: 3740732 (1973-06-01), Frandon
dennard et al., "Metal-Oxide-Semiconductor . . . Array . . . " I.B.M. Tech. Discl. Bull., vol. 10, No. 1, June 1967, pp. 77-78.
Landauer, R. W., "IGFET Decoders and Encoders" I.B.M. Tech. Discl. Bull., vol. 10, No. 1, June 1967, pp. 81-82.
"MOS Moves Onto High-Speed Track" Electronics, May 26, 1969, pp. 49-50.
Brown et al., "Self-Registered Molybdenum-Gate MOSFET" J. Electrochem. Soc., vol. 115, No. 8, Aug. 1968, pp. 874-876.
Matsushita Electronics Corporation
Rutledge L. Dewayne
Saba W. G.
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