Method of manufacturing of thin based substrate

Details Method of manufacturing of thin based substrate Method of manufacturing of thin based substrate

2006-05-23

2006-05-23

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S458000, C438S460000

Reexamination Certificate

active

07049208

ABSTRACT:
Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

REFERENCES:
patent: 2004/0229445 (2004-11-01), Suzuki et al.
patent: 2005/0003649 (2005-01-01), Takao
Thomas Dory, U.S. Appl. No. 10/832, 178, filed Apr. 26, 2004.
Terry Sterrett, U.S. Appl. No. 10/925,775, filed Aug. 25, 2004.
Terry Sterrett, U.S. Appl. No. 10/924,396, filed Aug. 23, 2004.
N. Tanaka et al. “Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module” Electronic Components and Technology Conference, IEEE 2003, pp. 473-479.
M. Tomisaka et al. “Electroplating Cu Fillings for Through-Vias for Three-Dimensional Chip Stacking” 2002 Electronic Components and Technology Conference, IEEE, pp. 14321-1438.
M. Umemoto et al. Superfine Flip-Chip Interconnection in 20um-Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI, 2002 Electronic Components and Technology Conference, IEEE, pp. 1454-1456.
N. Tanaka et al. “Guidelines for Structural and Material-System Design of a Highly Reliable 3D Die-Stacked Module with Copper Through-Vias” 2003 Electronic Components and Technology Conference, IEEE, pp. 597-602.
K. Tanida et al. “Ultra-High-Density 3D Chip Stacking Technology” 2003 Electronic Components and Technology Conference, IEEE, pp. 1084-1089.
M. Sunohara et al. “Development of Wafer Thinning and Double-Sided Bumping Technologies for the Three-Dimensional Stacked LSI” 2002 Electronic Components and Technology Conference, IEEE, pp. 238-245.
M. Umemoto et al. Non-Metallurgical Bonding Technology with Super-Narrow Gap for 3D Stacked LSI, 2002 Electronic Components and Technology Conference, IEEE, pp. 285-288.

Affiliated with

Also associated with

Rating

Method of manufacturing of thin based substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing of thin based substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing of thin based substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3613030