Fishing – trapping – and vermin destroying
Patent
1991-07-12
1992-12-15
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 34, 437 40, 437 52, 357 45, 357 50, H01L 2170, H01L 2700
Patent
active
051717018
ABSTRACT:
A method for forming in a short time master-slice integrated circuits of high reliability, which circuits comprise diffusion layers and polysilicon layers which form transistor elements, and a plurality of metal wiring layers formed for realizing desired circuits, with insulating layers interposed between every adjacent two of the wiring layers. The methods comprises a first wiring process in which a master slice is provided by forming a predetermined number of metal layers in a wafer, and a second wiring process in which further metal wiring layers, to be customized so as to have logical functions required by a user, are formed on the first-mentioned metal wiring layers. The inner-most metal wiring layer of all the metal layers is used as wide power source line which is almost free from electro or stress migration.
REFERENCES:
patent: 4388755 (1983-06-01), Enomoto et al.
patent: 4633571 (1987-01-01), Kolwicz
patent: 4682202 (1987-07-01), Tanizawa
patent: 4742383 (1988-05-01), Fitzgerald
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4791474 (1988-12-01), Sugiura et al.
patent: 4980745 (1990-12-01), Muroga
Hearn Brian E.
Kabushiki Kaisha Toshiba
Picardat Kevin M.
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