Method of manufacturing master-slice semiconductor integrated ci

Fishing – trapping – and vermin destroying

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437 34, 437 40, 437 52, 357 45, 357 50, H01L 2170, H01L 2700

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active

051717018

ABSTRACT:
A method for forming in a short time master-slice integrated circuits of high reliability, which circuits comprise diffusion layers and polysilicon layers which form transistor elements, and a plurality of metal wiring layers formed for realizing desired circuits, with insulating layers interposed between every adjacent two of the wiring layers. The methods comprises a first wiring process in which a master slice is provided by forming a predetermined number of metal layers in a wafer, and a second wiring process in which further metal wiring layers, to be customized so as to have logical functions required by a user, are formed on the first-mentioned metal wiring layers. The inner-most metal wiring layer of all the metal layers is used as wide power source line which is almost free from electro or stress migration.

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patent: 4980745 (1990-12-01), Muroga

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