Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-03-29
2011-03-29
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S781000, C257S786000, C257SE23194, C257SE23019, C257SE27111, C257SE21505, C257SE23173, C257SE23079, C257SE21569, C257SE21614, C257SE25006, C257SE25013, C257SE21018, C438S109000, C438S113000, C438S118000, C438S458000, C438S612000, C438S617000
Reexamination Certificate
active
07915079
ABSTRACT:
A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.
REFERENCES:
patent: 5953588 (1999-09-01), Camien et al.
patent: 7127807 (2006-10-01), Yamaguchi et al.
patent: 2007/0120243 (2007-05-01), Yanagisawa et al.
patent: 2009/0325345 (2009-12-01), Sasaki et al.
Gann, Keith D., “Neo-Stacking Technology,”HDI Magazine, Dec. 1999, pp. 1-4.
Iijima Atsushi
Ito Hiroyuki
Sasaki Yoshitaka
Abdelaziez Yasser A
Garber Charles D
Headway Technologies Inc.
Oliff & Berridg,e PLC
SAE Magnetics (H.K. ) Ltd.
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