Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
1999-10-12
2001-02-13
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
C438S238000, C438S619000
Reexamination Certificate
active
06187647
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
Not Applicable
FIELD OF THE INVENTION
This invention relates to the manufacturing of semiconductor devices. More specifically, the invention relates to a method of manufacturing a lateral inductor on a semiconductor device.
BACKGROUND OF THE INVENTION
High-Q inductors are a common feature found on most communications semiconductor devices. The most common method of forming an inductor in a semiconductor device involves depositing thick layers, 3 &mgr;m or greater, of metal on the top layer of circuitry. This top layer is formed in a spiral pattern in conjunction with a special substrate to create a high-Q inductor. This method has the disadvantage in that to create an inductor of
10
, an area of typically more than 300 &mgr;m×300 &mgr;m is required. This area subsequently cannot be used for other circuitry due to electromagnetic interference. Additionally, current processing techniques to form these high-Q inductors that use photoresist and copper require two or more mask levels and two or more exposure steps. This processing results in inductors with air gaps that are not compatible with current processing technology.
Previous attempts have been made at creating lateral high-Q inductors on either non-conducting or highly resistive substrates. However, current chip designs prefer highly conductive substrates for latch-up protection. Current versions of high-Q inductors on silicon substrates have been demonstrated with planar spiral inductors in AlCu, but this technology is not compatible with upper level copper metalization.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of forming a high-Q lateral inductor that provide reduced area requirements in a semiconductor device.
It is yet another object of the invention to provide a method of forming a high-Q lateral inductor that can be used with copper damascene processes.
It is another object of the invention to provide a method of forming a high-Q lateral inductor that only requires a single mask step.
It is a further object of the invention to provide a method of forming a high-Q lateral inductor that can be easily modeled using readily available analytical tools.
It is still another object of the invention is to provide a method of forming a high-Q lateral inductor that is CMOS compatible.
Yet another object of the invention is to provide a method of forming a high-Q lateral inductor that is compatible with silicon substrates.
These and other objects of the invention are achieved by the subject method of manufacturing a semiconductor device having a high-Q inductor. The method comprises the steps of forming the bottom legs on a first substrate; depositing a second substrate layer over the first substrate; forming the pair of side legs for each loop through the second substrate layer; and, forming top legs connecting pairs of side legs extending from adjacent bottom legs.
The step of forming the side legs preferably includes forming a pair of vias through the second substrate layer to the bottom legs, and depositing side legs in the vias. The step of forming the top legs preferably includes forming a channel between the pairs of vias respectively communicating with the adjacent bottom legs, and depositing top legs in the channels. Additionally, the steps of forming the side and top legs are performed concurrently.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are described below. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.
REFERENCES:
patent: 6008102 (1999-12-01), Alford et al.
patent: 6025261 (2000-02-01), Farrar et al.
patent: 6057202 (2000-05-01), Chen et al.
patent: 6083802 (1999-12-01), Wen et al.
Chaudhari Chandra
Lucent Technologies - Inc.
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