Method of manufacturing junction field effect transistors

Details Method of manufacturing junction field effect transistors Method of manufacturing junction field effect transistors

1977-10-25

1980-01-01

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 148175, 148188, 148190, 357 22, H01L 21225

Patent

active

041815424

ABSTRACT:
A vertical or horizontal type junction FET including a channel-gate structure formed by a double diffusion process in which two treatments for diffusing different impurities are executed through an identical opening provided in a diffusion mask. For fabricating a vertical type junction FET, such double diffusion process is applied to stacked upper and lower semi-conductor layers having opposite conducting types thereby forming a channel region adjacent to the upper semi-conductor layer which functions as a first gate region and forming a second gate region adjacent to the channel region and remote from the first gate region. For fabricating horizontal type junction FET, the double diffusion process stated above is applied to a single semi-conductor layer to form a first gate region thereby forming a channel region adjacent to the first gate region and a second gate region adjacent to the channel region and remote from the first gate region. In either type of junction FET's the width of each channel region is precisely determined and corresponds to the difference in the diffusion depths in the two diffusion treatments. Moreover, the impurity concentration and the concentration profile of each channel region is determined independently of those of the drain or source region. Furthermore in the manufacturing process of each FET, the second gate region is self aligned so as to overlap a corresponding channel region.

REFERENCES:
patent: 3472710 (1969-10-01), Welty
patent: 4030954 (1977-06-01), Horie
patent: 4049476 (1977-09-01), Horie

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