Fishing – trapping – and vermin destroying
Patent
1997-03-25
1998-01-27
Bowers, Jr., Charles L.
Fishing, trapping, and vermin destroying
437194, 437195, 437192, H01L 21283
Patent
active
057121400
ABSTRACT:
An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
REFERENCES:
patent: 4556897 (1985-12-01), Yorikane et al.
patent: 4816424 (1989-03-01), Watanabe et al.
patent: 4820611 (1989-04-01), Arnold, III et al.
patent: 4924295 (1990-05-01), Kuecher
patent: 4962060 (1990-10-01), Sliwa et al.
patent: 4980752 (1990-12-01), Jones, Jr.
patent: 4987099 (1991-01-01), Flanner
patent: 5066615 (1991-11-01), Brady et al.
patent: 5071714 (1991-12-01), Rodbell et al.
patent: 5082801 (1992-01-01), Nagata
patent: 5091328 (1992-02-01), Miller
patent: 5106786 (1992-04-01), Brady et al.
patent: 5231053 (1993-07-01), Bost et al.
patent: 5289035 (1994-02-01), Bost et al.
S. Wolf "Silicon Proc. For VLSI Era" 1990 pp. 132-3, 192-3, 252-3, 284-5.
S. Wolf, "Silicon Processing for the VLSI Era" vol. II, pp. 190-193, 252-253, 264-267, 280-285 Jun. 1990.
"A Highly Reliable Multilevel Interconnection Process for 0.6.mu.mCMOS Devices" by Y. Takata et al, 8th Inst. VLSI Multilevel Interconnection Conference, Santa Clara, CA, U.S.A., Jun. 11, 12, 1991, 7 pages.
Abstract Citation, Rodbell et al., Abstract for "Electromigration Behavior in Layered Ti/AlCu/Ti Films and Its Dependence on Intermetallic Structure.", publication appers in MATERIALS RELIABILITY ISSUES IN MICROELECTRONICS SYMPOSIUM, Mater. Res. Soc. 1991.
Ishii Atsushi
Maekawa Kazuyoshi
Ohsaki Akihiko
Takata Yoshifumi
Bowers Jr. Charles L.
Mitsubishi Denki & Kabushiki Kaisha
Radomsky Leon
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