Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-02-09
2001-06-05
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C356S237600, C382S145000, 36
Reexamination Certificate
active
06242270
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing integrated circuits as described in the precharacterizing part of claim
1
. The invention also relates to a system implementing said method.
Such a method is known from the abstract of Japanese patent application laid open number 5-259015 (1993).
Integrated circuits are manufactured by submitting wafers to a series of processing steps. During processing defects may occur on the wafer, which reduce the yield of properly functioning integrating circuits on the wafer. Malfunctioning apparatuses may increase the number of defects. The abstract of Japanese patent application laid open number 5-259015 (1993) proposes to count the number of defects such as particles or patterning errors on the wafer after a processing step. If the number of defects is to high, it is attempted to redo the processing step in order to remove the defects. If this is not possible, the wafer is discarded and the process conditions are adjusted before processing further wafers.
Such a method may be used in factory management system to increase the yield and to control the correction of malfunctioning apparatuses. However, if such a method is applied at each processing step to check for malfunctioning of the apparatus performing that processing step, the factory management system would become very expensive, even if it were possible without disturbing the processing steps. Moreover, in general there is no certainty that defects detected after a processing step are actually due to the apparatus performing that processing step: the defects might be due to apparatuses that perform earlier processing steps.
SUMMARY OF THE INVENTION
Amongst others, it is an object of the invention to provide for a method of manufacturing integrated circuits in which processing apparatuses that do not perform satisfactorily are detected without the need to detect defects at every processing step.
The method of manufacturing integrated circuits according to the invention is characterized by the characterizing part of claim 1. Herein “apparatuses” generally refer to devices that have an individual effect on integrated circuit wafers at some stage; as used herein, an apparatus may be a component of a system containing several such components. “processing steps” refer generally to tasks performed by the apparatuses.
Examples of different classes of defects that can be distinguished are scratches, particle contamination, lattice stacking faults, dripped liquid, focus errors, pinholes in patterns, bridges between patterns, poorly developed patterns, deviating linewidths, presence of flakes, Tungsten particles, Ti/TiN particles, Blocked etch, corrosion, missing contacts etc.
By counting defects of different classes separately after a number of processing steps, and by providing associations that automatically links different classes of defects to processing steps, it is possible to detect apparatuses that are suspected of not performing satisfactorily automatically and without exhaustive testing. When an apparatus is brought off-line, this is signalled to a process operator, who will adjust or repair the apparatus before bringing it on-line again.
Often several equivalent apparatuses are available performing at least one of the processing steps from a set of apparatuses capable of performing that at least one of the processing steps. In that case, one will keeping a record indicating which apparatus has performed the at least one of the processing steps on the wafer and select the apparatus that is brought off-line using said record when the at least one of the processing steps is associated with the particular class, the apparatus that is brought off-line being removed from said set, so that it will no longer be selected for performing the at least one processing step, at least until an adjustment has been made. Thus, the excess number of defects can be linked to a specific apparatus.
Another embodiment of the method according to the invention is described in claim 2. This embodiment provides for using a differential count, representing the increase in the number of defects due to a number of processing steps between defect counting at a first stage and defect counting at a second stage. The differential count is much more sensitive to defects caused by apparatuses performing processing steps between the second and first stage, and therefore apparatuses can be switched off-line more reliably.
A further embodiment of the method according to the invention is described in claim 3. By using a fraction of the defects detected at the second stage a reasonable estimate of the number of prior defects can be realized without serious intervention in the process.
Another embodiment of the method according to the invention is described in claim 4. Instead of counting defects individually, all defects in a cluster counted as one defect only. This prevents unnecessary switch-off due to a complicated local defect that hardly affects overall yield. If clusters are only a small fraction of the defects, one may even omit the defects in a cluster from the count entirely.
Another embodiment of the method according to the invention is described in claim 5. Basically, only the defect density, i.e. the number of defects per unit of area on the wafer needs to be known in order to decide about switching apparatuses off-line. By counting defects on part of the wafer only, the amount of time needed for counting may be reduced.
Another embodiment of the method according to the invention is described in claim 6. According to this embodiment visual defects are first detected irrespective of their class, from abnormalities in the wafers, which are detected for example by comparing image locations of one chip on the wafer with corresponding image locations for a neighboring chip, or of a known “good” chip. Subsequently, the defects that have been found are classified. The defects may be clustered before they are classified, to reduce the time needed for classification. In principle only a fraction of randomly selected abnormalities needs to be classified, if one uses the assumption that the total number of defects of each class is proportional to the total number of classified abnormalities divided by the fraction.
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Nagaswami Venkat R.
Van Gessel Johannes G.
Van Wezep Dries A.
Biren Steven R.
Luk Olivia
Tsai Jey
U.S. Phillips Corporation
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