Method of manufacturing InP junction FETS and junction HEMTS usi

Details Method of manufacturing InP junction FETS and junction HEMTS usi Method of manufacturing InP junction FETS and junction HEMTS usi

1989-12-29

1993-03-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 39, 437133, 437911, 437978, 748DIG43, 748DIG84, 748DIG88, H01L 21334

Patent

active

051963582

ABSTRACT:
A new planar, fully ion-implanted indium phosphide junction FET (JFET) fabrication process, utilizing n.sup.+ source-drain implantation, Be and Be/P p.sup.+ gate implantation, and nitride-registered gate metallization.

REFERENCES:
patent: H291 (1987-06-01), Boos
patent: 4196439 (1980-04-01), Niehans
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4727404 (1988-02-01), Boccon-Gibod
patent: 4816881 (1989-03-01), Boos et al.
patent: 4830980 (1989-05-01), Hsien
Boos et al., "Planar, Fully Ion-Implanted InP Junction FET's with a NitriRegistered Gate Metallization," IEEE Electron Device Letters, vol. 10, No. 2, Feb. 1989.
Boos, J. B., et al., IEEE Electron Device LEtters, vol. EDL-5, No. 7, Jul. 1984, pp. 273-276.
Alamo, J. A., et al., IEEE Transaction on Electron Devices, vol. 36, No. 4, Apr. 1989, pp. 646-650.

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