Method of manufacturing high capacity semiconductor capacitance

Details Method of manufacturing high capacity semiconductor capacitance Method of manufacturing high capacity semiconductor capacitance

1981-10-07

1985-03-26

Hearn, Brian E.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 29571, 29577C, 29578, 357 236, H01L 21265

Patent

active

045071594

ABSTRACT:
The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region.
One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant.
Another way of achieving the desired diffusion of first polarity dopant with respect to the second polarity dopant is to select the two dopants with diffusivities approximately equal and to diffuse the first polarity dopant before the second polarity dopants is implanted into the semiconductor substrate.

REFERENCES:
patent: 3945856 (1976-03-01), Koenig et al.
patent: 4112575 (1978-09-01), Fu et al.
patent: 4125933 (1978-11-01), Baldwin et al.

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