Method of manufacturing graded channels underneath the gate elec

Details Method of manufacturing graded channels underneath the gate elec Method of manufacturing graded channels underneath the gate elec

1994-10-24

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437 28, 437 34, 437 57, 437 58, 257336, H01L 21265

Patent

active

055061613

ABSTRACT:
Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (55) and a P-channel transistor (60). The N-channel transistor (55) has a gate electrode (22') that has a central portion (22) and gate electrode extensions (41) adjacent to the central portion (22). Likewise the P-channel transistor (60) has a gate electrode (24') that has a central portion (24) and gate electrode extensions (42) adjacent to the central portion (24). The gate electrode extensions (41, 42) are formed by filling openings (34, 36) with a gate electrode material. The openings are used for the formation of graded channel regions underneath the gate electrode extensions (41, 42).

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