Method of manufacturing flat panel backplanes including improved

Details Method of manufacturing flat panel backplanes including improved Method of manufacturing flat panel backplanes including improved

1986-12-31

1989-04-11

Ramsey, Kenneth J.

Electric lamp or space discharge component or device manufacturi

Process

With testing or adjusting

340784, 445 24, 437 8, G09G 322

Patent

active

048202223

ABSTRACT:
Subdivided pixels are provided with interconnected and hence redundant row and column bus lines to reduce fatal defects. The respective redundant row and column lines also can be interconnected between subpixels to further reduce defects. One defective subpixel is generally an acceptable non-fatal defect, since the rest of the subpixels are still operative. The subpixels also can be formed with common row and column bus lines. The pixels or subpixels can be connected in a serial serpentine pattern to test all row or all column bus lines at once. After testing, the serial connections are broken.

REFERENCES:
patent: 3701184 (1972-10-01), Grier
patent: 3707767 (1973-01-01), Quevrin
patent: 3940740 (1976-02-01), Coontz
patent: 4368523 (1983-01-01), Kawate
patent: 4586242 (1986-05-01), Harrison
patent: 4676761 (1987-06-01), Poujois
patent: 4680580 (1987-07-01), Kawahara

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