Method of manufacturing flash memory device

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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Details

C438S672000, C438S675000, C438S700000, C257SE21577, C257SE21585

Reexamination Certificate

active

07410881

ABSTRACT:
A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole. A second conductive material is formed on the contact plug and filling the upper portion of the contact hole to form a bit line.

REFERENCES:
patent: 2003/0071321 (2003-04-01), Hong
patent: 2005/0285177 (2005-12-01), Shone
patent: 2007/0020820 (2007-01-01), Chindalore et al.
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patent: 1020030042106 (2003-05-01), None
patent: 1020040080599 (2004-09-01), None
patent: 100645839 (2006-11-01), None
patent: 100734680 (2007-06-01), None

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