Method of manufacturing first and second memory cell arrays with

Details Method of manufacturing first and second memory cell arrays with Method of manufacturing first and second memory cell arrays with

1996-05-01

1997-03-18

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 48, 437 60, H01L 218247

Patent

active

056122381

ABSTRACT:
A DRAM includes a main section including a DRAM memory cell array including a plurality of DRAM cells arranged in an array, a spare section including a Spare DRAM memory cell array including a plurality of DRAM memory cells arranged in an array, an address decoder for specifying addresses respectively of the DRAM memory cell array and the spare DRAM memory cell array, and a defective bit replacement control circuit which is connected to the address decoder and which includes a plurality of electrically rewritable nonvolatile memory cells.

REFERENCES:
patent: 5262342 (1993-11-01), Toyama et al.
patent: 5290725 (1994-03-01), Tanaka et al.
patent: 5389567 (1995-02-01), Acovic et al.

Affiliated with

Also associated with

Rating

Method of manufacturing first and second memory cell arrays with does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing first and second memory cell arrays with, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing first and second memory cell arrays with will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1705789