Method of manufacturing ferroelectric memory device

Details Method of manufacturing ferroelectric memory device Method of manufacturing ferroelectric memory device

1999-09-24

2002-04-30

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S396000, C438S240000

Reexamination Certificate

active

06379977

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a ferroelectric memory device using a ferroelectric thin film as a dielectric layer of a capacitor.
2. Description of the Related Art
In general, in a ferroelectric memory device of nonvolatile memory devices, a ferroelectric thin film such as a SrBi
2
Ta
2
O
9
(SBT) layer and a Pb(ZrTi
1−x
)O
3
layer is mainly used as a dielectric layer of a capacitor. The properties of the ferroelectric thin film depend on materials for upper and lower electrodes of the capacitor, especially the lower electrode material. Accordingly, to obtain good properties of the ferroelectric thin film, the lower electrode is formed of a platinum(Pt) layer having a good oxidation resistance, a conductive oxide layer such as an IrO
2
layer or a RuO
2
layer, or a metal layer such as an iridium(Ir) or ruthenium(Ru). Of these, the Pt layer is mainly used.
In the ferroelectric memory device as described above, the capacitor is generally formed by forming the lower electrode, the ferroelectric thin film and the upper electrode on an intermediate insulating layer such as an oxide layer. Here, the lower electrode is formed of the Pt layer. Furthermore, since the adhesion between the Pt layer and oxide layer is poor, a titanium(Ti) layer is interposed therebetween as a glue layer, for improving the adhesion.
However, when performing thermal processes under oxygen atmosphere subsequently after forming the Pt layer as the lower electrode, Ti is diffused into the Pt layer, thereby deteriorating the adhesion between the Ti layer and the intermediate insulating layer. Furthermore, Ti is oxidized in the Pt layer to form a titanium oxide layer. Therefore, the volume of the Pt layer is expanded so that the surface roughness of the lower layer is deteriorated, thereby deteriorating the reliability and the yield of device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to a method of manufacturing a ferroelectric memory device which can improve the adhesion between an intermediate insulating layer and a lower electrode and the surface roughness of the lower electrode, for solving the problems in the conventional art.
To accomplish this above object, according to a first embodiment of the present invention, a titanium layer and a first platinum layer are sequentially formed on a semiconductor substrate on which a first intermediate insulating layer is formed. The substrate is then thermal-treated under oxygen atmosphere to transform the titanium layer and the first platinum layer into a titanium oxide layer containing platinum. Next, a second platinum layer for a lower electrode, a ferroelectric thin film and a third platinum layer for an upper electrode are formed on the titanium oxide layer containing platinum, in sequence. The third platinum layer is then etched to form the upper electrode. Next, the ferroelectric thin film, the second platinum layer and the titanium oxide layer containing platinum are etched to form a capacitor.
In the first embodiment, the total thickness of the titanium and the first platinum layers is 100 to 300 Å. The first platinum layer has a quarter thickness of the titanium layer to a thickness as the titanium layer. Furthermore, the thermal-treating is performed at the temperature 650 to 800° C. for 1 minute by rapid thermal process.
According to a second embodiment of the present invention, a titanium layer and a first platinum layer are sequentially formed on a semiconductor substrate on which a first intermediate insulating layer is formed. The substrate is then thermal-treated under the atmosphere of N
2
gas or inert gas by a first thermal process to react the titanium layer with the first platinum layer, thereby forming a platinum titanium (Pt
x
Ti
y
) alloy layer. Next, the substrate is thermal-treated under oxygen atmosphere by a second thermal process, to prevent titanium not reacted during the first thermal process from diffusing. A ferroelectric thin film is then formed on the platinum titanium alloy layer. The ferroelectric thin film and the platinum titanium alloy layer are then etched to form a ferroelectric thin film pattern and a lower electrode. Thereafter, a capping layer is formed on the overall substrate so as to expose the ferroelectric thin film pattern. An upper electrode is then formed on the exposed ferroelectric thin film pattern, thereby forming the capacitor.
In the second embodiment, the first platinum layer is formed by in-situ after forming the titanium layer. The titanium layer is formed to the thickness of 50 to 500 Å and the first platinum layer is formed to the thickness of 1,000 to 3,000 Å. Furthermore, the first thermal process is performed at the temperature of 400 to 600° C. for 10 minutes to 2 hours by furnace and the second thermal process is performed at the temperature of 600 to 800° C. for 10 minutes to 2 hours. Moreover, the capping layer is formed of a silicon oxide layer.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 5340607 (1994-08-01), Friz et al.
patent: 5431958 (1995-07-01), Desu et al.
patent: 5554564 (1996-09-01), Nishioka et al.
patent: 5554866 (1996-09-01), Nishioka et al.
patent: 5589284 (1996-12-01), Summerfelt et al.
patent: 5626906 (1997-05-01), Summerfelt et al.
patent: 5683614 (1997-11-01), Boyle
patent: 5742076 (1998-04-01), Sridevan et al.
patent: 5750419 (1998-05-01), Zafar
patent: 5850089 (1998-12-01), Varshney et al.
patent: 5851896 (1998-12-01), Summerfelt
patent: 5858851 (1999-01-01), Yamagata et al.
patent: 5882946 (1999-03-01), Otani
patent: 5912044 (1999-06-01), Farooq et al.
patent: 6004857 (1999-12-01), Hsiao et al.
patent: 6010940 (2000-01-01), Lee et al.
patent: 6022774 (2000-02-01), Kawai et al.
patent: 0448151 (1991-09-01), None
patent: 0720213 (1996-03-01), None
patent: 03019372 (1991-01-01), None
patent: 08340084 (1996-12-01), None
patent: 9153597 (1997-06-01), None
patent: 10012844 (1998-01-01), None
patent: 9634407 (1996-10-01), None
patent: 9641375 (1996-12-01), None
patent: 9735339 (1997-09-01), None

Affiliated with

Also associated with

Rating

Method of manufacturing ferroelectric memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing ferroelectric memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing ferroelectric memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2897533