Chemistry: analytical and immunological testing – Optical result – With reagent in absorbent or bibulous substrate
Reexamination Certificate
2000-08-10
2002-11-05
Ho, Hoai (Department: 2818)
Chemistry: analytical and immunological testing
Optical result
With reagent in absorbent or bibulous substrate
C438S622000, C438S637000
Reexamination Certificate
active
06475810
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to an improved ultra large-scale integrated (ULSI) circuit having an embedded organic stop layer. More particularly, the present invention relates to the fabrication of ULSI using a dual damascene process in conjunction with an embedded organic stop layer.
2. Description of Prior Art
The dual damascene process, in which metal interconnect is buried inside patterned grooves in a substrate, is frequently used and has become one of the best methods for fabricating USLI circuits Conventionally, metallic interconnects are formed by depositing a metallic layer over an insulating layer, for example, a silicon dioxide layer. Then, the insulating layer is etched to form a pattern of predefined conductive lines so that a vertical via hole can be formed between conductive layers. Thereafter, metallic material is deposited into the via hole to complete vertical connection between the conductive layers.
Workers in the art are aware that the metallic layer at the bottom of the via hole is exposed and unprotected, and therefore will be etched in the process of forming the via hole. Consequently, the metallic layer can be easily damaged resulting in a change in device properties, and ultimately even not being able to use the device is possible. Others have striven to solve this and other problems. For example U.S. Pat. No. 5,989,997 (Lin et al.) shows leaving a portion of the photo-resist remaining at the bottom of the via hole. U.S. Pat. No. 6,007,733 (Jang, et al.), U.S. Pat. No. 6,004,883 (Yu, et al.), and U.S. Pat. No. 5,741,626 (Jain, et al.) all show dual damascene processes. U.S. Pat. No. 5,882,996 (Dai) teaches a dual damascene method with etch stops and an ARC interstitial layer. Finally, U.S. Pat. No. 5,874,201 (Licata, et al.) shows a dual damascene using a spin on organic layer over the ILD layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for forming a dual damascene interconnect structure, wherein damage during etching is minimized by embedding an organic stop layer over the lower interconnect and later etching the organic stop layer with H2 plasma.
The present invention is a method for forming a dual damascene opening by providing a semiconductor structure, and forming a dielectric layer having an interconnect over the substrate semiconductor structure. Then in a critical step, we form an organic stop layer over the dielectric layer and the interconnect. Then we form second and third dielectric layers in sequence to form a stack dielectric layer over the organic stop layer. Finally, patterning the stack dielectric layers to form a dual damascene opening exposing the organic stop layer and using the organic stop layer as a protective cover for the interconnect, and then removing the organic stop layer to expose said interconnect. In an preferred embodiment a H
2
containing plasma is used to remover the remove the organic stop layer to expose said interconnect.
In another aspect of the invention the need for PEC (post etch-cleaning) and PDC (pre-deposition-cleaning) can be eliminated.
The invention's organic stop layer and H
2
containing plasma finishing etch step provide many advantages over the prior art. The invention's organic stop layer prevents etch damage to the underlying interconnect during the etching of the stack dielectric layers to form the damascene opening. The invention's H
2
plasma effectively removes the organic stop layer without damaging the underlying interconnect. Also when copper is used as the conductor in the underlying interconnect, the present invention prevents contamination to the ILD/IMD layers due to sputtering of copper onto the via sidewalls.
REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 5874201 (1999-02-01), Licata et al.
patent: 5882996 (1999-03-01), Dai
patent: 5989997 (1999-11-01), Lin et al.
patent: 6004883 (1999-12-01), Yu et al.
patent: 6007733 (1999-12-01), Jang et al.
patent: 6040243 (2000-03-01), Li et al.
patent: 6066569 (2000-05-01), Tobben
patent: 6127089 (2000-10-01), Subramanian et al.
patent: 6165891 (2000-12-01), Chooi et al.
Aliyu Yakub
Chooi Simon
Gupta Subhash
Ho Paul Kwok Keung
Roy Sudipto Ranendra
Chartered Semiconductor Manufacturing Ltd.
Ho Hoai
Le Dung A
Pike Rosemary L. S.
Saile George O.
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