Method of manufacturing electronic device, substrate and...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S118000, C438S613000, C257SE21170, C257SE21237, C257SE21499, C257SE21502, C257SE21508

Reexamination Certificate

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07829378

ABSTRACT:
A method includes a step of forming a bump104having a projection104B on an electrode pad103provided on a semiconductor chip101, a step of exposing a part of the projection104B to an upper surface of an insulating layer105formed on the semiconductor chip101, a step of forming a conductive layer107A on the upper surface of the insulating layer105and an exposed part of a tip portion104D, a step of removing a protruded portion of the conductive layer107A which is opposed to the tip portion104D by means of a grinding roll112, thereby exposing the projection from the conductive layer107A, and a step of forming a conductive layer108A through electrolytic plating using the conductive layer107A as a feeding layer and patterning the conductive layer108A.

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patent: 5929521 (1999-07-01), Wark et al.
patent: 6809421 (2004-10-01), Hayasaka et al.
patent: 7492945 (2009-02-01), Yamazaki et al.
patent: 7649369 (2010-01-01), Okumura et al.
patent: 2004/0238927 (2004-12-01), Miyazawa
patent: 2009/0035929 (2009-02-01), Yuzawa et al.
patent: 2002-313985 (2002-10-01), None

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