Method of manufacturing EEPROM memory device with a select gate

Details Method of manufacturing EEPROM memory device with a select gate Method of manufacturing EEPROM memory device with a select gate

1994-10-11

1995-08-29

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437984, H01L 218247

Patent

active

054459834

ABSTRACT:
A method is provided for fabricating an MOSFET device on a lightly doped semiconductor substrate. A first dielectric layer on the substrate is patterned with a select gate channel opening therein. Sacrificial spacer structures are formed adjacent to the edges of the channel opening in the first dielectric layer. A gate oxide layer is formed at the base of the opening, followed by a select gate for a select transistor over the gate oxide layer between the spacer structures in the channel opening. The sacrificial spacer structures are removed exposing the substrate to form trenches between the first dielectric layer and the select gate. A pair of select transistor doped source/drain regions in the substrate are formed to define the select transistor channel using the select gate and the first dielectric layer as a self-aligned mask. Removal of the first dielectric layer exposes the substrate surrounding the select gate, followed by forming a thin silicon dioxide layer over the select gate and the substrate, and a floating gate conductor over the select gate and a portion thereof in contact with one of the thin silicon dioxide layers, an interconductor dielectric layer over the floating gate conductor, a control gate structure over the interconductor dielectric layer, and ion implanting a pair of stacked gate doped source/drain regions in the substrate.

REFERENCES:
patent: 5049516 (1991-09-01), Arima
patent: 5081054 (1992-01-01), Wu et al.
patent: 5100818 (1992-03-01), Arima et al.
patent: 5364806 (1994-11-01), Ma et al.
Ajika et al., "A Novel Cell Structure for 4 MBit Full Feature EEPROM and Beyond" IEEE IEDM pp. 295-298 (1991).

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