Fishing – trapping – and vermin destroying
Patent
1995-06-06
1998-08-11
Niebling, John
Fishing, trapping, and vermin destroying
437 44, 437 45, H01L 218247, H01L 21265
Patent
active
057926700
ABSTRACT:
A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.
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Pio Federico
Riva Carlo
Booth Richard A.
Carlson David V.
Niebling John
Santarelli Bryan A.
SGS--Thomson Microelectronics S.r.l.
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